Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
DMA Channel 0 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 CTRL register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 4 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 4 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 4 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 4 Control and Status
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 4 CTRL register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 4 READ_ADDR register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 4 WRITE_ADDR register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 4 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 4 CTRL register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 4 TRANS_COUNT register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 4 READ_ADDR register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 4 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 4 CTRL register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 4 WRITE_ADDR register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 4 TRANS_COUNT register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 4 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 READ_ADDR register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 5 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 5 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 5 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 5 Control and Status
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 5 CTRL register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 5 READ_ADDR register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 5 WRITE_ADDR register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 5 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 5 CTRL register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 5 TRANS_COUNT register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 5 READ_ADDR register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 5 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 5 CTRL register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 5 WRITE_ADDR register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 5 TRANS_COUNT register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 5 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 WRITE_ADDR register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 6 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 6 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 6 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 6 Control and Status
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 6 CTRL register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 6 READ_ADDR register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 6 WRITE_ADDR register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 6 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 6 CTRL register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 6 TRANS_COUNT register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 6 READ_ADDR register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 6 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 6 CTRL register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 6 WRITE_ADDR register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 6 TRANS_COUNT register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 6 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 7 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 7 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 7 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 7 Control and Status
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 7 CTRL register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 7 READ_ADDR register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 7 WRITE_ADDR register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 7 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 7 CTRL register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 7 TRANS_COUNT register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 7 READ_ADDR register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 7 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 7 CTRL register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 7 WRITE_ADDR register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 7 TRANS_COUNT register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 7 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 CTRL register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 8 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 8 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 8 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 8 Control and Status
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 8 CTRL register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 8 READ_ADDR register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 8 WRITE_ADDR register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 8 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 8 CTRL register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 8 TRANS_COUNT register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 8 READ_ADDR register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 8 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 8 CTRL register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 8 WRITE_ADDR register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 8 TRANS_COUNT register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 8 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 TRANS_COUNT register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 9 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 9 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 9 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 9 Control and Status
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 9 CTRL register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 9 READ_ADDR register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 9 WRITE_ADDR register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 9 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 9 CTRL register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 9 TRANS_COUNT register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 9 READ_ADDR register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 9 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 9 CTRL register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 9 WRITE_ADDR register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 9 TRANS_COUNT register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 9 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 READ_ADDR register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 10 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 10 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 10 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 10 Control and Status
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 10 CTRL register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 10 READ_ADDR register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 10 WRITE_ADDR register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 10 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 10 CTRL register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 10 TRANS_COUNT register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 10 READ_ADDR register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 10 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 10 CTRL register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 10 WRITE_ADDR register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 10 TRANS_COUNT register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 10 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 11 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 11 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 11 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 11 Control and Status
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 11 CTRL register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 11 READ_ADDR register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 11 WRITE_ADDR register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 11 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 11 CTRL register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 11 TRANS_COUNT register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 11 READ_ADDR register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 11 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 11 CTRL register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 11 WRITE_ADDR register
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 11 TRANS_COUNT register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 11 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 CTRL register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 WRITE_ADDR register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 TRANS_COUNT register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 0 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 0 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 1 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt Status (raw)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR : Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.
Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.
This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.
It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.
bits : 0 - 15 (16 bit)
access : read-only
Interrupt Enables for IRQ 0
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTE0 : Set bit n to pass interrupts from channel n to DMA IRQ 0.
bits : 0 - 15 (16 bit)
access : read-write
Force Interrupts
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTF0 : Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Status for IRQ 0
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.
Channel interrupts can be cleared by writing a bit mask here.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Enables for IRQ 1
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTE1 : Set bit n to pass interrupts from channel n to DMA IRQ 1.
bits : 0 - 15 (16 bit)
access : read-write
Force Interrupts for IRQ 1
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTF1 : Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Status (masked) for IRQ 1
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS1 : Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.
Channel interrupts can be cleared by writing a bit mask here.
bits : 0 - 15 (16 bit)
access : read-write
Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y : Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
bits : 0 - 15 (16 bit)
access : read-write
X : Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
bits : 16 - 31 (16 bit)
access : read-write
Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y : Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
bits : 0 - 15 (16 bit)
access : read-write
X : Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
bits : 16 - 31 (16 bit)
access : read-write
Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
address_offset : 0x428 Bytes (0x0)
size : 32 bit
reset_value : 0x0
Y : Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
bits : 0 - 15 (16 bit)
access : read-write
X : Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
bits : 16 - 31 (16 bit)
access : read-write
Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
address_offset : 0x42C Bytes (0x0)
size : 32 bit
reset_value : 0x0
Y : Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
bits : 0 - 15 (16 bit)
access : read-write
X : Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
bits : 16 - 31 (16 bit)
access : read-write
Trigger one or more channels simultaneously
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MULTI_CHAN_TRIGGER : Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register the channel will start if it is currently enabled and not already busy.
bits : 0 - 15 (16 bit)
access : read-write
Sniffer Control
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable sniffer
bits : 0 - 0 (1 bit)
access : read-write
DMACH : DMA channel for Sniffer to observe
bits : 1 - 4 (4 bit)
access : read-write
CALC :
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0 : CRC32
Calculate a CRC-32 (IEEE802.3 polynomial)
1 : CRC32R
Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data
2 : CRC16
Calculate a CRC-16-CCITT
3 : CRC16R
Calculate a CRC-16-CCITT with bit reversed data
14 : EVEN
XOR reduction over all data. == 1 if the total 1 population count is odd.
15 : SUM
Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)
End of enumeration elements list.
BSWAP : Locally perform a byte reverse on the sniffed data, before feeding into checksum.
Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view.
bits : 9 - 9 (1 bit)
access : read-write
OUT_REV : If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated the result is transformed on-the-fly between the result register and the bus.
bits : 10 - 10 (1 bit)
access : read-write
OUT_INV : If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated the result is transformed on-the-fly between the result register and the bus.
bits : 11 - 11 (1 bit)
access : read-write
Data accumulator for sniff hardware
Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 1 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Debug RAF, WAF, TDF levels
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDF_LVL : Current Transfer-Data-FIFO fill level
bits : 0 - 7 (8 bit)
access : read-only
WAF_LVL : Current Write-Address-FIFO fill level
bits : 8 - 15 (8 bit)
access : read-only
RAF_LVL : Current Read-Address-FIFO fill level
bits : 16 - 23 (8 bit)
access : read-only
Abort an in-progress transfer sequence on one or more channels
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHAN_ABORT : Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.
After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.
bits : 0 - 15 (16 bit)
access : read-write
The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
N_CHANNELS :
bits : 0 - 4 (5 bit)
access : read-only
DMA Channel 1 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 1 Control and Status
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 1 CTRL register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 1 READ_ADDR register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 1 WRITE_ADDR register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 1 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 1 CTRL register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 1 TRANS_COUNT register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 1 READ_ADDR register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 1 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 1 CTRL register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 1 WRITE_ADDR register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 1 TRANS_COUNT register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 1 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 0 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 2 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 2 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 2 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x884 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 2 Control and Status
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 CTRL register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 READ_ADDR register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x944 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 WRITE_ADDR register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x984 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x9C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x9C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 CTRL register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xA04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 TRANS_COUNT register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xA40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xA44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 READ_ADDR register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xA80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xAC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xAC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 CTRL register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 WRITE_ADDR register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 TRANS_COUNT register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 2 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 0 Control and Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
DMA Channel 3 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 3 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 3 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel 3 Control and Status
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
None
1 : SIZE_HALFWORD
None
2 : SIZE_WORD
None
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 5 - 5 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
None
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 10 - 10 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
bits : 11 - 14 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 15 - 20 (6 bit)
access : read-write
Enumeration:
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 21 - 21 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 22 - 22 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 23 - 23 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 24 - 24 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 3 CTRL register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 3 READ_ADDR register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 3 WRITE_ADDR register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 3 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 3 CTRL register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 3 TRANS_COUNT register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 3 READ_ADDR register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 3 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 3 CTRL register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 3 WRITE_ADDR register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 3 TRANS_COUNT register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Alias for channel 3 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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