\n

PIO0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

TXF0

SM2_SHIFTCTRL

SM2_ADDR

SM2_INSTR

SM2_PINCTRL

SM3_CLKDIV

SM3_EXECCTRL

SM3_SHIFTCTRL

SM3_ADDR

SM3_INSTR

SM3_PINCTRL

INTR

IRQ0_INTE

IRQ0_INTF

IRQ0_INTS

IRQ1_INTE

IRQ1_INTF

TXF1

IRQ1_INTS

TXF2

TXF3

RXF0

RXF1

RXF2

RXF3

IRQ

IRQ_FORCE

INPUT_SYNC_BYPASS

DBG_PADOUT

FSTAT

DBG_PADOE

DBG_CFGINFO

INSTR_MEM0

INSTR_MEM1

INSTR_MEM2

INSTR_MEM3

INSTR_MEM4

INSTR_MEM5

INSTR_MEM6

INSTR_MEM7

INSTR_MEM8

INSTR_MEM9

INSTR_MEM10

INSTR_MEM11

INSTR_MEM12

INSTR_MEM13

FDEBUG

INSTR_MEM14

INSTR_MEM15

INSTR_MEM16

INSTR_MEM17

INSTR_MEM18

INSTR_MEM19

INSTR_MEM20

INSTR_MEM21

INSTR_MEM22

INSTR_MEM23

INSTR_MEM24

INSTR_MEM25

INSTR_MEM26

INSTR_MEM27

INSTR_MEM28

INSTR_MEM29

FLEVEL

INSTR_MEM30

INSTR_MEM31

SM0_CLKDIV

SM0_EXECCTRL

SM0_SHIFTCTRL

SM0_ADDR

SM0_INSTR

SM0_PINCTRL

SM1_CLKDIV

SM1_EXECCTRL

SM1_SHIFTCTRL

SM1_ADDR

SM1_INSTR

SM1_PINCTRL

SM2_CLKDIV

SM2_EXECCTRL


CTRL

PIO control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM_ENABLE SM_RESTART CLKDIV_RESTART

SM_ENABLE : Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.
bits : 0 - 3 (4 bit)
access : read-write

SM_RESTART : Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters the contents of the input shift register the delay counter the waiting-on-IRQ state any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC any pin write left asserted due to OUT_STICKY.
bits : 4 - 7 (4 bit)
access : read-write

CLKDIV_RESTART : Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.
bits : 8 - 11 (4 bit)
access : read-write


TXF0

Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXF0 TXF0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SM2_SHIFTCTRL

Control behaviour of the input/output shift registers for state machine 2
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM2_SHIFTCTRL SM2_SHIFTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTOPUSH AUTOPULL IN_SHIFTDIR OUT_SHIFTDIR PUSH_THRESH PULL_THRESH FJOIN_TX FJOIN_RX

AUTOPUSH : Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
bits : 16 - 16 (1 bit)
access : read-write

AUTOPULL : Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
bits : 17 - 17 (1 bit)
access : read-write

IN_SHIFTDIR : 1 = shift input shift register to right (data enters from left). 0 = to left.
bits : 18 - 18 (1 bit)
access : read-write

OUT_SHIFTDIR : 1 = shift out of output shift register to right. 0 = to left.
bits : 19 - 19 (1 bit)
access : read-write

PUSH_THRESH : Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32.
bits : 20 - 24 (5 bit)
access : read-write

PULL_THRESH : Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32.
bits : 25 - 29 (5 bit)
access : read-write

FJOIN_TX : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
bits : 30 - 30 (1 bit)
access : read-write

FJOIN_RX : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
bits : 31 - 31 (1 bit)
access : read-write


SM2_ADDR

Current instruction address of state machine 2
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM2_ADDR SM2_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM2_ADDR

SM2_ADDR :
bits : 0 - 4 (5 bit)
access : read-only


SM2_INSTR

Read to see the instruction currently addressed by state machine 2's program counter Write to execute an instruction immediately (including jumps) and then resume execution.
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM2_INSTR SM2_INSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM2_INSTR

SM2_INSTR :
bits : 0 - 15 (16 bit)
access : read-write


SM2_PINCTRL

State machine pin control
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM2_PINCTRL SM2_PINCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_BASE SET_BASE SIDESET_BASE IN_BASE OUT_COUNT SET_COUNT SIDESET_COUNT

OUT_BASE : The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
bits : 0 - 4 (5 bit)
access : read-write

SET_BASE : The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
bits : 5 - 9 (5 bit)
access : read-write

SIDESET_BASE : The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
bits : 10 - 14 (5 bit)
access : read-write

IN_BASE : The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
bits : 15 - 19 (5 bit)
access : read-write

OUT_COUNT : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
bits : 20 - 25 (6 bit)
access : read-write

SET_COUNT : The number of pins asserted by a SET. In the range 0 to 5 inclusive.
bits : 26 - 28 (3 bit)
access : read-write

SIDESET_COUNT : The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
bits : 29 - 31 (3 bit)
access : read-write


SM3_CLKDIV

Clock divisor register for state machine 3 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM3_CLKDIV SM3_CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC : Fractional part of clock divisor
bits : 8 - 15 (8 bit)
access : read-write

INT : Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
bits : 16 - 31 (16 bit)
access : read-write


SM3_EXECCTRL

Execution/behavioural settings for state machine 3
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM3_EXECCTRL SM3_EXECCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_N STATUS_SEL WRAP_BOTTOM WRAP_TOP OUT_STICKY INLINE_OUT_EN OUT_EN_SEL JMP_PIN SIDE_PINDIR SIDE_EN EXEC_STALLED

STATUS_N : Comparison level for the MOV x, STATUS instruction
bits : 0 - 3 (4 bit)
access : read-write

STATUS_SEL : Comparison used for the MOV x, STATUS instruction.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : TXLEVEL

All-ones if TX FIFO level < N, otherwise all-zeroes

1 : RXLEVEL

All-ones if RX FIFO level < N, otherwise all-zeroes

End of enumeration elements list.

WRAP_BOTTOM : After reaching wrap_top, execution is wrapped to this address.
bits : 7 - 11 (5 bit)
access : read-write

WRAP_TOP : After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority.
bits : 12 - 16 (5 bit)
access : read-write

OUT_STICKY : Continuously assert the most recent OUT/SET to the pins
bits : 17 - 17 (1 bit)
access : read-write

INLINE_OUT_EN : If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
bits : 18 - 18 (1 bit)
access : read-write

OUT_EN_SEL : Which data bit to use for inline OUT enable
bits : 19 - 23 (5 bit)
access : read-write

JMP_PIN : The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
bits : 24 - 28 (5 bit)
access : read-write

SIDE_PINDIR : If 1, side-set data is asserted to pin directions, instead of pin values
bits : 29 - 29 (1 bit)
access : read-write

SIDE_EN : If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
bits : 30 - 30 (1 bit)
access : read-write

EXEC_STALLED : If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
bits : 31 - 31 (1 bit)
access : read-only


SM3_SHIFTCTRL

Control behaviour of the input/output shift registers for state machine 3
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM3_SHIFTCTRL SM3_SHIFTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTOPUSH AUTOPULL IN_SHIFTDIR OUT_SHIFTDIR PUSH_THRESH PULL_THRESH FJOIN_TX FJOIN_RX

AUTOPUSH : Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
bits : 16 - 16 (1 bit)
access : read-write

AUTOPULL : Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
bits : 17 - 17 (1 bit)
access : read-write

IN_SHIFTDIR : 1 = shift input shift register to right (data enters from left). 0 = to left.
bits : 18 - 18 (1 bit)
access : read-write

OUT_SHIFTDIR : 1 = shift out of output shift register to right. 0 = to left.
bits : 19 - 19 (1 bit)
access : read-write

PUSH_THRESH : Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32.
bits : 20 - 24 (5 bit)
access : read-write

PULL_THRESH : Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32.
bits : 25 - 29 (5 bit)
access : read-write

FJOIN_TX : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
bits : 30 - 30 (1 bit)
access : read-write

FJOIN_RX : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
bits : 31 - 31 (1 bit)
access : read-write


SM3_ADDR

Current instruction address of state machine 3
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM3_ADDR SM3_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM3_ADDR

SM3_ADDR :
bits : 0 - 4 (5 bit)
access : read-only


SM3_INSTR

Read to see the instruction currently addressed by state machine 3's program counter Write to execute an instruction immediately (including jumps) and then resume execution.
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM3_INSTR SM3_INSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM3_INSTR

SM3_INSTR :
bits : 0 - 15 (16 bit)
access : read-write


SM3_PINCTRL

State machine pin control
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM3_PINCTRL SM3_PINCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_BASE SET_BASE SIDESET_BASE IN_BASE OUT_COUNT SET_COUNT SIDESET_COUNT

OUT_BASE : The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
bits : 0 - 4 (5 bit)
access : read-write

SET_BASE : The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
bits : 5 - 9 (5 bit)
access : read-write

SIDESET_BASE : The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
bits : 10 - 14 (5 bit)
access : read-write

IN_BASE : The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
bits : 15 - 19 (5 bit)
access : read-write

OUT_COUNT : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
bits : 20 - 25 (6 bit)
access : read-write

SET_COUNT : The number of pins asserted by a SET. In the range 0 to 5 inclusive.
bits : 26 - 28 (3 bit)
access : read-write

SIDESET_COUNT : The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
bits : 29 - 31 (3 bit)
access : read-write


INTR

Raw Interrupts
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM0_RXNEMPTY SM1_RXNEMPTY SM2_RXNEMPTY SM3_RXNEMPTY SM0_TXNFULL SM1_TXNFULL SM2_TXNFULL SM3_TXNFULL SM0 SM1 SM2 SM3

SM0_RXNEMPTY :
bits : 0 - 0 (1 bit)
access : read-only

SM1_RXNEMPTY :
bits : 1 - 1 (1 bit)
access : read-only

SM2_RXNEMPTY :
bits : 2 - 2 (1 bit)
access : read-only

SM3_RXNEMPTY :
bits : 3 - 3 (1 bit)
access : read-only

SM0_TXNFULL :
bits : 4 - 4 (1 bit)
access : read-only

SM1_TXNFULL :
bits : 5 - 5 (1 bit)
access : read-only

SM2_TXNFULL :
bits : 6 - 6 (1 bit)
access : read-only

SM3_TXNFULL :
bits : 7 - 7 (1 bit)
access : read-only

SM0 :
bits : 8 - 8 (1 bit)
access : read-only

SM1 :
bits : 9 - 9 (1 bit)
access : read-only

SM2 :
bits : 10 - 10 (1 bit)
access : read-only

SM3 :
bits : 11 - 11 (1 bit)
access : read-only


IRQ0_INTE

Interrupt Enable for irq0
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ0_INTE IRQ0_INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM0_RXNEMPTY SM1_RXNEMPTY SM2_RXNEMPTY SM3_RXNEMPTY SM0_TXNFULL SM1_TXNFULL SM2_TXNFULL SM3_TXNFULL SM0 SM1 SM2 SM3

SM0_RXNEMPTY :
bits : 0 - 0 (1 bit)
access : read-write

SM1_RXNEMPTY :
bits : 1 - 1 (1 bit)
access : read-write

SM2_RXNEMPTY :
bits : 2 - 2 (1 bit)
access : read-write

SM3_RXNEMPTY :
bits : 3 - 3 (1 bit)
access : read-write

SM0_TXNFULL :
bits : 4 - 4 (1 bit)
access : read-write

SM1_TXNFULL :
bits : 5 - 5 (1 bit)
access : read-write

SM2_TXNFULL :
bits : 6 - 6 (1 bit)
access : read-write

SM3_TXNFULL :
bits : 7 - 7 (1 bit)
access : read-write

SM0 :
bits : 8 - 8 (1 bit)
access : read-write

SM1 :
bits : 9 - 9 (1 bit)
access : read-write

SM2 :
bits : 10 - 10 (1 bit)
access : read-write

SM3 :
bits : 11 - 11 (1 bit)
access : read-write


IRQ0_INTF

Interrupt Force for irq0
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ0_INTF IRQ0_INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM0_RXNEMPTY SM1_RXNEMPTY SM2_RXNEMPTY SM3_RXNEMPTY SM0_TXNFULL SM1_TXNFULL SM2_TXNFULL SM3_TXNFULL SM0 SM1 SM2 SM3

SM0_RXNEMPTY :
bits : 0 - 0 (1 bit)
access : read-write

SM1_RXNEMPTY :
bits : 1 - 1 (1 bit)
access : read-write

SM2_RXNEMPTY :
bits : 2 - 2 (1 bit)
access : read-write

SM3_RXNEMPTY :
bits : 3 - 3 (1 bit)
access : read-write

SM0_TXNFULL :
bits : 4 - 4 (1 bit)
access : read-write

SM1_TXNFULL :
bits : 5 - 5 (1 bit)
access : read-write

SM2_TXNFULL :
bits : 6 - 6 (1 bit)
access : read-write

SM3_TXNFULL :
bits : 7 - 7 (1 bit)
access : read-write

SM0 :
bits : 8 - 8 (1 bit)
access : read-write

SM1 :
bits : 9 - 9 (1 bit)
access : read-write

SM2 :
bits : 10 - 10 (1 bit)
access : read-write

SM3 :
bits : 11 - 11 (1 bit)
access : read-write


IRQ0_INTS

Interrupt status after masking & forcing for irq0
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ0_INTS IRQ0_INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM0_RXNEMPTY SM1_RXNEMPTY SM2_RXNEMPTY SM3_RXNEMPTY SM0_TXNFULL SM1_TXNFULL SM2_TXNFULL SM3_TXNFULL SM0 SM1 SM2 SM3

SM0_RXNEMPTY :
bits : 0 - 0 (1 bit)
access : read-only

SM1_RXNEMPTY :
bits : 1 - 1 (1 bit)
access : read-only

SM2_RXNEMPTY :
bits : 2 - 2 (1 bit)
access : read-only

SM3_RXNEMPTY :
bits : 3 - 3 (1 bit)
access : read-only

SM0_TXNFULL :
bits : 4 - 4 (1 bit)
access : read-only

SM1_TXNFULL :
bits : 5 - 5 (1 bit)
access : read-only

SM2_TXNFULL :
bits : 6 - 6 (1 bit)
access : read-only

SM3_TXNFULL :
bits : 7 - 7 (1 bit)
access : read-only

SM0 :
bits : 8 - 8 (1 bit)
access : read-only

SM1 :
bits : 9 - 9 (1 bit)
access : read-only

SM2 :
bits : 10 - 10 (1 bit)
access : read-only

SM3 :
bits : 11 - 11 (1 bit)
access : read-only


IRQ1_INTE

Interrupt Enable for irq1
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ1_INTE IRQ1_INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM0_RXNEMPTY SM1_RXNEMPTY SM2_RXNEMPTY SM3_RXNEMPTY SM0_TXNFULL SM1_TXNFULL SM2_TXNFULL SM3_TXNFULL SM0 SM1 SM2 SM3

SM0_RXNEMPTY :
bits : 0 - 0 (1 bit)
access : read-write

SM1_RXNEMPTY :
bits : 1 - 1 (1 bit)
access : read-write

SM2_RXNEMPTY :
bits : 2 - 2 (1 bit)
access : read-write

SM3_RXNEMPTY :
bits : 3 - 3 (1 bit)
access : read-write

SM0_TXNFULL :
bits : 4 - 4 (1 bit)
access : read-write

SM1_TXNFULL :
bits : 5 - 5 (1 bit)
access : read-write

SM2_TXNFULL :
bits : 6 - 6 (1 bit)
access : read-write

SM3_TXNFULL :
bits : 7 - 7 (1 bit)
access : read-write

SM0 :
bits : 8 - 8 (1 bit)
access : read-write

SM1 :
bits : 9 - 9 (1 bit)
access : read-write

SM2 :
bits : 10 - 10 (1 bit)
access : read-write

SM3 :
bits : 11 - 11 (1 bit)
access : read-write


IRQ1_INTF

Interrupt Force for irq1
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ1_INTF IRQ1_INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM0_RXNEMPTY SM1_RXNEMPTY SM2_RXNEMPTY SM3_RXNEMPTY SM0_TXNFULL SM1_TXNFULL SM2_TXNFULL SM3_TXNFULL SM0 SM1 SM2 SM3

SM0_RXNEMPTY :
bits : 0 - 0 (1 bit)
access : read-write

SM1_RXNEMPTY :
bits : 1 - 1 (1 bit)
access : read-write

SM2_RXNEMPTY :
bits : 2 - 2 (1 bit)
access : read-write

SM3_RXNEMPTY :
bits : 3 - 3 (1 bit)
access : read-write

SM0_TXNFULL :
bits : 4 - 4 (1 bit)
access : read-write

SM1_TXNFULL :
bits : 5 - 5 (1 bit)
access : read-write

SM2_TXNFULL :
bits : 6 - 6 (1 bit)
access : read-write

SM3_TXNFULL :
bits : 7 - 7 (1 bit)
access : read-write

SM0 :
bits : 8 - 8 (1 bit)
access : read-write

SM1 :
bits : 9 - 9 (1 bit)
access : read-write

SM2 :
bits : 10 - 10 (1 bit)
access : read-write

SM3 :
bits : 11 - 11 (1 bit)
access : read-write


TXF1

Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXF1 TXF1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ1_INTS

Interrupt status after masking & forcing for irq1
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ1_INTS IRQ1_INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM0_RXNEMPTY SM1_RXNEMPTY SM2_RXNEMPTY SM3_RXNEMPTY SM0_TXNFULL SM1_TXNFULL SM2_TXNFULL SM3_TXNFULL SM0 SM1 SM2 SM3

SM0_RXNEMPTY :
bits : 0 - 0 (1 bit)
access : read-only

SM1_RXNEMPTY :
bits : 1 - 1 (1 bit)
access : read-only

SM2_RXNEMPTY :
bits : 2 - 2 (1 bit)
access : read-only

SM3_RXNEMPTY :
bits : 3 - 3 (1 bit)
access : read-only

SM0_TXNFULL :
bits : 4 - 4 (1 bit)
access : read-only

SM1_TXNFULL :
bits : 5 - 5 (1 bit)
access : read-only

SM2_TXNFULL :
bits : 6 - 6 (1 bit)
access : read-only

SM3_TXNFULL :
bits : 7 - 7 (1 bit)
access : read-only

SM0 :
bits : 8 - 8 (1 bit)
access : read-only

SM1 :
bits : 9 - 9 (1 bit)
access : read-only

SM2 :
bits : 10 - 10 (1 bit)
access : read-only

SM3 :
bits : 11 - 11 (1 bit)
access : read-only


TXF2

Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXF2 TXF2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXF3

Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXF3 TXF3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXF0

Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXF0 RXF0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXF1

Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXF1 RXF1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXF2

Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXF2 RXF2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXF3

Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXF3 RXF3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ

State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ IRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ

IRQ :
bits : 0 - 7 (8 bit)
access : read-write


IRQ_FORCE

Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ_FORCE IRQ_FORCE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ_FORCE

IRQ_FORCE :
bits : 0 - 7 (8 bit)
access : write-only


INPUT_SYNC_BYPASS

There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INPUT_SYNC_BYPASS INPUT_SYNC_BYPASS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DBG_PADOUT

Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DBG_PADOUT DBG_PADOUT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FSTAT

FIFO status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSTAT FSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFULL RXEMPTY TXFULL TXEMPTY

RXFULL : State machine RX FIFO is full
bits : 0 - 3 (4 bit)
access : read-only

RXEMPTY : State machine RX FIFO is empty
bits : 8 - 11 (4 bit)
access : read-only

TXFULL : State machine TX FIFO is full
bits : 16 - 19 (4 bit)
access : read-only

TXEMPTY : State machine TX FIFO is empty
bits : 24 - 27 (4 bit)
access : read-only


DBG_PADOE

Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DBG_PADOE DBG_PADOE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DBG_CFGINFO

The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBG_CFGINFO DBG_CFGINFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_DEPTH SM_COUNT IMEM_SIZE

FIFO_DEPTH : The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth.
bits : 0 - 5 (6 bit)
access : read-only

SM_COUNT : The number of state machines this PIO instance is equipped with.
bits : 8 - 11 (4 bit)
access : read-only

IMEM_SIZE : The size of the instruction memory, measured in units of one instruction
bits : 16 - 21 (6 bit)
access : read-only


INSTR_MEM0

Write-only access to instruction memory location 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM0 INSTR_MEM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM0

INSTR_MEM0 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM1

Write-only access to instruction memory location 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM1 INSTR_MEM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM1

INSTR_MEM1 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM2

Write-only access to instruction memory location 2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM2 INSTR_MEM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM2

INSTR_MEM2 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM3

Write-only access to instruction memory location 3
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM3 INSTR_MEM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM3

INSTR_MEM3 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM4

Write-only access to instruction memory location 4
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM4 INSTR_MEM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM4

INSTR_MEM4 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM5

Write-only access to instruction memory location 5
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM5 INSTR_MEM5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM5

INSTR_MEM5 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM6

Write-only access to instruction memory location 6
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM6 INSTR_MEM6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM6

INSTR_MEM6 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM7

Write-only access to instruction memory location 7
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM7 INSTR_MEM7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM7

INSTR_MEM7 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM8

Write-only access to instruction memory location 8
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM8 INSTR_MEM8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM8

INSTR_MEM8 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM9

Write-only access to instruction memory location 9
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM9 INSTR_MEM9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM9

INSTR_MEM9 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM10

Write-only access to instruction memory location 10
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM10 INSTR_MEM10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM10

INSTR_MEM10 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM11

Write-only access to instruction memory location 11
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM11 INSTR_MEM11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM11

INSTR_MEM11 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM12

Write-only access to instruction memory location 12
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM12 INSTR_MEM12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM12

INSTR_MEM12 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM13

Write-only access to instruction memory location 13
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM13 INSTR_MEM13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM13

INSTR_MEM13 :
bits : 0 - 15 (16 bit)
access : write-only


FDEBUG

FIFO debug register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDEBUG FDEBUG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXSTALL RXUNDER TXOVER TXSTALL

RXSTALL : State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.
bits : 0 - 3 (4 bit)
access : read-write

RXUNDER : RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.
bits : 8 - 11 (4 bit)
access : read-write

TXOVER : TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.
bits : 16 - 19 (4 bit)
access : read-write

TXSTALL : State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.
bits : 24 - 27 (4 bit)
access : read-write


INSTR_MEM14

Write-only access to instruction memory location 14
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM14 INSTR_MEM14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM14

INSTR_MEM14 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM15

Write-only access to instruction memory location 15
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM15 INSTR_MEM15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM15

INSTR_MEM15 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM16

Write-only access to instruction memory location 16
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM16 INSTR_MEM16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM16

INSTR_MEM16 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM17

Write-only access to instruction memory location 17
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM17 INSTR_MEM17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM17

INSTR_MEM17 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM18

Write-only access to instruction memory location 18
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM18 INSTR_MEM18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM18

INSTR_MEM18 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM19

Write-only access to instruction memory location 19
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM19 INSTR_MEM19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM19

INSTR_MEM19 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM20

Write-only access to instruction memory location 20
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM20 INSTR_MEM20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM20

INSTR_MEM20 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM21

Write-only access to instruction memory location 21
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM21 INSTR_MEM21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM21

INSTR_MEM21 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM22

Write-only access to instruction memory location 22
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM22 INSTR_MEM22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM22

INSTR_MEM22 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM23

Write-only access to instruction memory location 23
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM23 INSTR_MEM23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM23

INSTR_MEM23 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM24

Write-only access to instruction memory location 24
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM24 INSTR_MEM24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM24

INSTR_MEM24 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM25

Write-only access to instruction memory location 25
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM25 INSTR_MEM25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM25

INSTR_MEM25 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM26

Write-only access to instruction memory location 26
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM26 INSTR_MEM26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM26

INSTR_MEM26 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM27

Write-only access to instruction memory location 27
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM27 INSTR_MEM27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM27

INSTR_MEM27 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM28

Write-only access to instruction memory location 28
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM28 INSTR_MEM28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM28

INSTR_MEM28 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM29

Write-only access to instruction memory location 29
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM29 INSTR_MEM29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM29

INSTR_MEM29 :
bits : 0 - 15 (16 bit)
access : write-only


FLEVEL

FIFO levels
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLEVEL FLEVEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX0 RX0 TX1 RX1 TX2 RX2 TX3 RX3

TX0 :
bits : 0 - 3 (4 bit)
access : read-only

RX0 :
bits : 4 - 7 (4 bit)
access : read-only

TX1 :
bits : 8 - 11 (4 bit)
access : read-only

RX1 :
bits : 12 - 15 (4 bit)
access : read-only

TX2 :
bits : 16 - 19 (4 bit)
access : read-only

RX2 :
bits : 20 - 23 (4 bit)
access : read-only

TX3 :
bits : 24 - 27 (4 bit)
access : read-only

RX3 :
bits : 28 - 31 (4 bit)
access : read-only


INSTR_MEM30

Write-only access to instruction memory location 30
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM30 INSTR_MEM30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM30

INSTR_MEM30 :
bits : 0 - 15 (16 bit)
access : write-only


INSTR_MEM31

Write-only access to instruction memory location 31
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTR_MEM31 INSTR_MEM31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR_MEM31

INSTR_MEM31 :
bits : 0 - 15 (16 bit)
access : write-only


SM0_CLKDIV

Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM0_CLKDIV SM0_CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC : Fractional part of clock divisor
bits : 8 - 15 (8 bit)
access : read-write

INT : Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
bits : 16 - 31 (16 bit)
access : read-write


SM0_EXECCTRL

Execution/behavioural settings for state machine 0
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM0_EXECCTRL SM0_EXECCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_N STATUS_SEL WRAP_BOTTOM WRAP_TOP OUT_STICKY INLINE_OUT_EN OUT_EN_SEL JMP_PIN SIDE_PINDIR SIDE_EN EXEC_STALLED

STATUS_N : Comparison level for the MOV x, STATUS instruction
bits : 0 - 3 (4 bit)
access : read-write

STATUS_SEL : Comparison used for the MOV x, STATUS instruction.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : TXLEVEL

All-ones if TX FIFO level < N, otherwise all-zeroes

1 : RXLEVEL

All-ones if RX FIFO level < N, otherwise all-zeroes

End of enumeration elements list.

WRAP_BOTTOM : After reaching wrap_top, execution is wrapped to this address.
bits : 7 - 11 (5 bit)
access : read-write

WRAP_TOP : After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority.
bits : 12 - 16 (5 bit)
access : read-write

OUT_STICKY : Continuously assert the most recent OUT/SET to the pins
bits : 17 - 17 (1 bit)
access : read-write

INLINE_OUT_EN : If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
bits : 18 - 18 (1 bit)
access : read-write

OUT_EN_SEL : Which data bit to use for inline OUT enable
bits : 19 - 23 (5 bit)
access : read-write

JMP_PIN : The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
bits : 24 - 28 (5 bit)
access : read-write

SIDE_PINDIR : If 1, side-set data is asserted to pin directions, instead of pin values
bits : 29 - 29 (1 bit)
access : read-write

SIDE_EN : If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
bits : 30 - 30 (1 bit)
access : read-write

EXEC_STALLED : If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
bits : 31 - 31 (1 bit)
access : read-only


SM0_SHIFTCTRL

Control behaviour of the input/output shift registers for state machine 0
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM0_SHIFTCTRL SM0_SHIFTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTOPUSH AUTOPULL IN_SHIFTDIR OUT_SHIFTDIR PUSH_THRESH PULL_THRESH FJOIN_TX FJOIN_RX

AUTOPUSH : Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
bits : 16 - 16 (1 bit)
access : read-write

AUTOPULL : Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
bits : 17 - 17 (1 bit)
access : read-write

IN_SHIFTDIR : 1 = shift input shift register to right (data enters from left). 0 = to left.
bits : 18 - 18 (1 bit)
access : read-write

OUT_SHIFTDIR : 1 = shift out of output shift register to right. 0 = to left.
bits : 19 - 19 (1 bit)
access : read-write

PUSH_THRESH : Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32.
bits : 20 - 24 (5 bit)
access : read-write

PULL_THRESH : Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32.
bits : 25 - 29 (5 bit)
access : read-write

FJOIN_TX : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
bits : 30 - 30 (1 bit)
access : read-write

FJOIN_RX : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
bits : 31 - 31 (1 bit)
access : read-write


SM0_ADDR

Current instruction address of state machine 0
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM0_ADDR SM0_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM0_ADDR

SM0_ADDR :
bits : 0 - 4 (5 bit)
access : read-only


SM0_INSTR

Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution.
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM0_INSTR SM0_INSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM0_INSTR

SM0_INSTR :
bits : 0 - 15 (16 bit)
access : read-write


SM0_PINCTRL

State machine pin control
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM0_PINCTRL SM0_PINCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_BASE SET_BASE SIDESET_BASE IN_BASE OUT_COUNT SET_COUNT SIDESET_COUNT

OUT_BASE : The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
bits : 0 - 4 (5 bit)
access : read-write

SET_BASE : The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
bits : 5 - 9 (5 bit)
access : read-write

SIDESET_BASE : The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
bits : 10 - 14 (5 bit)
access : read-write

IN_BASE : The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
bits : 15 - 19 (5 bit)
access : read-write

OUT_COUNT : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
bits : 20 - 25 (6 bit)
access : read-write

SET_COUNT : The number of pins asserted by a SET. In the range 0 to 5 inclusive.
bits : 26 - 28 (3 bit)
access : read-write

SIDESET_COUNT : The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
bits : 29 - 31 (3 bit)
access : read-write


SM1_CLKDIV

Clock divisor register for state machine 1 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM1_CLKDIV SM1_CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC : Fractional part of clock divisor
bits : 8 - 15 (8 bit)
access : read-write

INT : Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
bits : 16 - 31 (16 bit)
access : read-write


SM1_EXECCTRL

Execution/behavioural settings for state machine 1
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM1_EXECCTRL SM1_EXECCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_N STATUS_SEL WRAP_BOTTOM WRAP_TOP OUT_STICKY INLINE_OUT_EN OUT_EN_SEL JMP_PIN SIDE_PINDIR SIDE_EN EXEC_STALLED

STATUS_N : Comparison level for the MOV x, STATUS instruction
bits : 0 - 3 (4 bit)
access : read-write

STATUS_SEL : Comparison used for the MOV x, STATUS instruction.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : TXLEVEL

All-ones if TX FIFO level < N, otherwise all-zeroes

1 : RXLEVEL

All-ones if RX FIFO level < N, otherwise all-zeroes

End of enumeration elements list.

WRAP_BOTTOM : After reaching wrap_top, execution is wrapped to this address.
bits : 7 - 11 (5 bit)
access : read-write

WRAP_TOP : After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority.
bits : 12 - 16 (5 bit)
access : read-write

OUT_STICKY : Continuously assert the most recent OUT/SET to the pins
bits : 17 - 17 (1 bit)
access : read-write

INLINE_OUT_EN : If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
bits : 18 - 18 (1 bit)
access : read-write

OUT_EN_SEL : Which data bit to use for inline OUT enable
bits : 19 - 23 (5 bit)
access : read-write

JMP_PIN : The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
bits : 24 - 28 (5 bit)
access : read-write

SIDE_PINDIR : If 1, side-set data is asserted to pin directions, instead of pin values
bits : 29 - 29 (1 bit)
access : read-write

SIDE_EN : If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
bits : 30 - 30 (1 bit)
access : read-write

EXEC_STALLED : If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
bits : 31 - 31 (1 bit)
access : read-only


SM1_SHIFTCTRL

Control behaviour of the input/output shift registers for state machine 1
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM1_SHIFTCTRL SM1_SHIFTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTOPUSH AUTOPULL IN_SHIFTDIR OUT_SHIFTDIR PUSH_THRESH PULL_THRESH FJOIN_TX FJOIN_RX

AUTOPUSH : Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
bits : 16 - 16 (1 bit)
access : read-write

AUTOPULL : Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
bits : 17 - 17 (1 bit)
access : read-write

IN_SHIFTDIR : 1 = shift input shift register to right (data enters from left). 0 = to left.
bits : 18 - 18 (1 bit)
access : read-write

OUT_SHIFTDIR : 1 = shift out of output shift register to right. 0 = to left.
bits : 19 - 19 (1 bit)
access : read-write

PUSH_THRESH : Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32.
bits : 20 - 24 (5 bit)
access : read-write

PULL_THRESH : Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32.
bits : 25 - 29 (5 bit)
access : read-write

FJOIN_TX : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
bits : 30 - 30 (1 bit)
access : read-write

FJOIN_RX : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
bits : 31 - 31 (1 bit)
access : read-write


SM1_ADDR

Current instruction address of state machine 1
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM1_ADDR SM1_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM1_ADDR

SM1_ADDR :
bits : 0 - 4 (5 bit)
access : read-only


SM1_INSTR

Read to see the instruction currently addressed by state machine 1's program counter Write to execute an instruction immediately (including jumps) and then resume execution.
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM1_INSTR SM1_INSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM1_INSTR

SM1_INSTR :
bits : 0 - 15 (16 bit)
access : read-write


SM1_PINCTRL

State machine pin control
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM1_PINCTRL SM1_PINCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_BASE SET_BASE SIDESET_BASE IN_BASE OUT_COUNT SET_COUNT SIDESET_COUNT

OUT_BASE : The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
bits : 0 - 4 (5 bit)
access : read-write

SET_BASE : The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
bits : 5 - 9 (5 bit)
access : read-write

SIDESET_BASE : The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
bits : 10 - 14 (5 bit)
access : read-write

IN_BASE : The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
bits : 15 - 19 (5 bit)
access : read-write

OUT_COUNT : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
bits : 20 - 25 (6 bit)
access : read-write

SET_COUNT : The number of pins asserted by a SET. In the range 0 to 5 inclusive.
bits : 26 - 28 (3 bit)
access : read-write

SIDESET_COUNT : The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
bits : 29 - 31 (3 bit)
access : read-write


SM2_CLKDIV

Clock divisor register for state machine 2 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM2_CLKDIV SM2_CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC : Fractional part of clock divisor
bits : 8 - 15 (8 bit)
access : read-write

INT : Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
bits : 16 - 31 (16 bit)
access : read-write


SM2_EXECCTRL

Execution/behavioural settings for state machine 2
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM2_EXECCTRL SM2_EXECCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS_N STATUS_SEL WRAP_BOTTOM WRAP_TOP OUT_STICKY INLINE_OUT_EN OUT_EN_SEL JMP_PIN SIDE_PINDIR SIDE_EN EXEC_STALLED

STATUS_N : Comparison level for the MOV x, STATUS instruction
bits : 0 - 3 (4 bit)
access : read-write

STATUS_SEL : Comparison used for the MOV x, STATUS instruction.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : TXLEVEL

All-ones if TX FIFO level < N, otherwise all-zeroes

1 : RXLEVEL

All-ones if RX FIFO level < N, otherwise all-zeroes

End of enumeration elements list.

WRAP_BOTTOM : After reaching wrap_top, execution is wrapped to this address.
bits : 7 - 11 (5 bit)
access : read-write

WRAP_TOP : After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority.
bits : 12 - 16 (5 bit)
access : read-write

OUT_STICKY : Continuously assert the most recent OUT/SET to the pins
bits : 17 - 17 (1 bit)
access : read-write

INLINE_OUT_EN : If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
bits : 18 - 18 (1 bit)
access : read-write

OUT_EN_SEL : Which data bit to use for inline OUT enable
bits : 19 - 23 (5 bit)
access : read-write

JMP_PIN : The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
bits : 24 - 28 (5 bit)
access : read-write

SIDE_PINDIR : If 1, side-set data is asserted to pin directions, instead of pin values
bits : 29 - 29 (1 bit)
access : read-write

SIDE_EN : If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
bits : 30 - 30 (1 bit)
access : read-write

EXEC_STALLED : If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
bits : 31 - 31 (1 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.