SYST_CSR

SYST_RVR

SYST_CVR

SYST_CALIB

NVIC_ISER

NVIC_ICER

NVIC_ISPR

NVIC_ICPR

NVIC_IPR0

NVIC_IPR1

NVIC_IPR2

NVIC_IPR3

NVIC_IPR4

NVIC_IPR5

NVIC_IPR6

NVIC_IPR7

CPUID

ICSR

VTOR

AIRCR

SCR

CCR

SHPR2

SHPR3

SHCSR

MPU_TYPE

MPU_CTRL

MPU_RNR

MPU_RBAR

MPU_RASR

ENABLE : Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled.
bits : 0 - 0 (1 bit)
access : read-write

TICKINT : Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request.
bits : 1 - 1 (1 bit)
access : read-write

CLKSOURCE : SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock.
bits : 2 - 2 (1 bit)
access : read-write

COUNTFLAG : Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.
bits : 16 - 16 (1 bit)
access : read-only

RELOAD : Value to load into the SysTick Current Value Register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write

CURRENT : Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
bits : 0 - 23 (24 bit)
access : read-write

TENMS : An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.
bits : 0 - 23 (24 bit)
access : read-only

SKEW : If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).
bits : 30 - 30 (1 bit)
access : read-only

NOREF : If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.
bits : 31 - 31 (1 bit)
access : read-only

SETENA : Interrupt set-enable bits. Write: 0 = No effect. 1 = Enable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled.
bits : 0 - 31 (32 bit)
access : read-write

CLRENA : Interrupt clear-enable bits. Write: 0 = No effect. 1 = Disable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled.
bits : 0 - 31 (32 bit)
access : read-write

SETPEND : Interrupt set-pending bits. Write: 0 = No effect. 1 = Changes interrupt state to pending. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending. Note: Writing 1 to the NVIC_ISPR bit corresponding to: An interrupt that is pending has no effect. A disabled interrupt sets the state of that interrupt to pending.
bits : 0 - 31 (32 bit)
access : read-write

CLRPEND : Interrupt clear-pending bits. Write: 0 = No effect. 1 = Removes pending state and interrupt. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending.
bits : 0 - 31 (32 bit)
access : read-write

IP_0 : Priority of interrupt 0
bits : 6 - 7 (2 bit)
access : read-write

IP_1 : Priority of interrupt 1
bits : 14 - 15 (2 bit)
access : read-write

IP_2 : Priority of interrupt 2
bits : 22 - 23 (2 bit)
access : read-write

IP_3 : Priority of interrupt 3
bits : 30 - 31 (2 bit)
access : read-write

IP_4 : Priority of interrupt 4
bits : 6 - 7 (2 bit)
access : read-write

IP_5 : Priority of interrupt 5
bits : 14 - 15 (2 bit)
access : read-write

IP_6 : Priority of interrupt 6
bits : 22 - 23 (2 bit)
access : read-write

IP_7 : Priority of interrupt 7
bits : 30 - 31 (2 bit)
access : read-write

IP_8 : Priority of interrupt 8
bits : 6 - 7 (2 bit)
access : read-write

IP_9 : Priority of interrupt 9
bits : 14 - 15 (2 bit)
access : read-write

IP_10 : Priority of interrupt 10
bits : 22 - 23 (2 bit)
access : read-write

IP_11 : Priority of interrupt 11
bits : 30 - 31 (2 bit)
access : read-write

IP_12 : Priority of interrupt 12
bits : 6 - 7 (2 bit)
access : read-write

IP_13 : Priority of interrupt 13
bits : 14 - 15 (2 bit)
access : read-write

IP_14 : Priority of interrupt 14
bits : 22 - 23 (2 bit)
access : read-write

IP_15 : Priority of interrupt 15
bits : 30 - 31 (2 bit)
access : read-write

IP_16 : Priority of interrupt 16
bits : 6 - 7 (2 bit)
access : read-write

IP_17 : Priority of interrupt 17
bits : 14 - 15 (2 bit)
access : read-write

IP_18 : Priority of interrupt 18
bits : 22 - 23 (2 bit)
access : read-write

IP_19 : Priority of interrupt 19
bits : 30 - 31 (2 bit)
access : read-write

IP_20 : Priority of interrupt 20
bits : 6 - 7 (2 bit)
access : read-write

IP_21 : Priority of interrupt 21
bits : 14 - 15 (2 bit)
access : read-write

IP_22 : Priority of interrupt 22
bits : 22 - 23 (2 bit)
access : read-write

IP_23 : Priority of interrupt 23
bits : 30 - 31 (2 bit)
access : read-write

IP_24 : Priority of interrupt 24
bits : 6 - 7 (2 bit)
access : read-write

IP_25 : Priority of interrupt 25
bits : 14 - 15 (2 bit)
access : read-write

IP_26 : Priority of interrupt 26
bits : 22 - 23 (2 bit)
access : read-write

IP_27 : Priority of interrupt 27
bits : 30 - 31 (2 bit)
access : read-write

IP_28 : Priority of interrupt 28
bits : 6 - 7 (2 bit)
access : read-write

IP_29 : Priority of interrupt 29
bits : 14 - 15 (2 bit)
access : read-write

IP_30 : Priority of interrupt 30
bits : 22 - 23 (2 bit)
access : read-write

IP_31 : Priority of interrupt 31
bits : 30 - 31 (2 bit)
access : read-write

REVISION : Minor revision number m in the rnpm revision status: 0x1 = Patch 1.
bits : 0 - 3 (4 bit)
access : read-only

PARTNO : Number of processor within family: 0xC60 = Cortex-M0+
bits : 4 - 15 (12 bit)
access : read-only

ARCHITECTURE : Constant that defines the architecture of the processor: 0xC = ARMv6-M architecture.
bits : 16 - 19 (4 bit)
access : read-only

VARIANT : Major revision number n in the rnpm revision status: 0x0 = Revision 0.
bits : 20 - 23 (4 bit)
access : read-only

IMPLEMENTER : Implementor code: 0x41 = ARM
bits : 24 - 31 (8 bit)
access : read-only

VECTACTIVE : Active exception number field. Reset clears the VECTACTIVE field.
bits : 0 - 8 (9 bit)
access : read-only

VECTPENDING : Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.
bits : 12 - 20 (9 bit)
access : read-only

ISRPENDING : External interrupt pending flag
bits : 22 - 22 (1 bit)
access : read-only

ISRPREEMPT : The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.
bits : 23 - 23 (1 bit)
access : read-only

PENDSTCLR : SysTick exception clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown.
bits : 25 - 25 (1 bit)
access : read-write

PENDSTSET : SysTick exception set-pending bit. Write: 0 = No effect. 1 = Changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending. 1 = SysTick exception is pending.
bits : 26 - 26 (1 bit)
access : read-write

PENDSVCLR : PendSV clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the PendSV exception.
bits : 27 - 27 (1 bit)
access : read-write

PENDSVSET : PendSV set-pending bit. Write: 0 = No effect. 1 = Changes PendSV exception state to pending. Read: 0 = PendSV exception is not pending. 1 = PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending.
bits : 28 - 28 (1 bit)
access : read-write

NMIPENDSET : Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. NMI set-pending bit. Write: 0 = No effect. 1 = Changes NMI exception state to pending. Read: 0 = NMI exception is not pending. 1 = NMI exception is pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
bits : 31 - 31 (1 bit)
access : read-write

TBLOFF : Bits [31:8] of the indicate the vector table offset address.
bits : 8 - 31 (24 bit)
access : read-write

VECTCLRACTIVE : Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.
bits : 1 - 1 (1 bit)
access : read-write

SYSRESETREQ : Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.
bits : 2 - 2 (1 bit)
access : read-write

ENDIANESS : Data endianness implemented: 0 = Little-endian.
bits : 15 - 15 (1 bit)
access : read-only

VECTKEY : Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.
bits : 16 - 31 (16 bit)
access : read-write

SLEEPONEXIT : Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write

SLEEPDEEP : Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep.
bits : 2 - 2 (1 bit)
access : read-write

SEVONPEND : Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write

UNALIGN_TRP : Always reads as one, indicates that all unaligned accesses generate a HardFault.
bits : 3 - 3 (1 bit)
access : read-only

STKALIGN : Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.
bits : 9 - 9 (1 bit)
access : read-only

PRI_11 : Priority of system handler 11, SVCall
bits : 30 - 31 (2 bit)
access : read-write

PRI_14 : Priority of system handler 14, PendSV
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of system handler 15, SysTick
bits : 30 - 31 (2 bit)
access : read-write

SVCALLPENDED : Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall.
bits : 15 - 15 (1 bit)
access : read-write

SEPARATE : Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU.
bits : 0 - 0 (1 bit)
access : read-only

DREGION : Number of regions supported by the MPU.
bits : 8 - 15 (8 bit)
access : read-only

IREGION : Instruction region. Reads as zero as ARMv6-M only supports a unified MPU.
bits : 16 - 23 (8 bit)
access : read-only

ENABLE : Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 0 = MPU disabled. 1 = MPU enabled.
bits : 0 - 0 (1 bit)
access : read-write

HFNMIENA : Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. When the MPU is enabled: 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. 1 = the MPU is enabled during HardFault and NMI handlers.
bits : 1 - 1 (1 bit)
access : read-write

PRIVDEFENA : Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.
bits : 2 - 2 (1 bit)
access : read-write

REGION : Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7.
bits : 0 - 3 (4 bit)
access : read-write

REGION : On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.
bits : 0 - 3 (4 bit)
access : read-write

VALID : On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. Write: 0 = MPU_RNR not changed, and the processor: Updates the base address for the region specified in the MPU_RNR. Ignores the value of the REGION field. 1 = The processor: Updates the value of the MPU_RNR to the value of the REGION field. Updates the base address for the region specified in the REGION field. Always reads as zero.
bits : 4 - 4 (1 bit)
access : read-write

ADDR : Base address of the region.
bits : 8 - 31 (24 bit)
access : read-write

ENABLE : Enables the region.
bits : 0 - 0 (1 bit)
access : read-write

SIZE : Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes
bits : 1 - 5 (5 bit)
access : read-write

SRD : Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.
bits : 8 - 15 (8 bit)
access : read-write

ATTRS : The MPU Region Attribute field. Use to define the region attribute control. 28 = XN: Instruction access disable bit: 0 = Instruction fetches enabled. 1 = Instruction fetches disabled. 26:24 = AP: Access permission field 18 = S: Shareable bit 17 = C: Cacheable bit 16 = B: Bufferable bit
bits : 16 - 31 (16 bit)
access : read-write