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AONCLOCK

Peripheral Memory Blocks

Registers

lfrosccfg


lfrosccfg

AON Clock Configuration Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

lfrosccfg lfrosccfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 div trim enable ready

div :
bits : 0 - -1 (0 bit)

trim :
bits : 16 - 36 (21 bit)

enable :
bits : 30 - 29 (0 bit)

ready :
bits : 31 - 30 (0 bit)



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