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PMU

Peripheral Memory Blocks

Registers

pmuie

pmucause

pmusleep

pmukey

pmuwakepm[0]

pmusleeppm[0]

pmuwakepm[1]

pmusleeppm[1]

pmuwakepm[2]

pmusleeppm[2]

pmuwakepm[3]

pmusleeppm[3]

pmuwakepm[4]

pmusleeppm[4]

pmuwakepm[5]

pmusleeppm[5]

pmuwakepm[6]

pmusleeppm[6]

pmuwakepm[7]

pmusleeppm[7]


pmuie

PMU Interrupt Enable Register
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmuie pmuie read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rtc dwakeup awakeup

rtc :
bits : 1 - 0 (0 bit)

dwakeup :
bits : 2 - 1 (0 bit)

awakeup :
bits : 3 - 2 (0 bit)


pmucause

PMU Cause Register
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmucause pmucause read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wakeupcause resetcause

wakeupcause :
bits : 0 - -1 (0 bit)

Enumeration:

0 : Reset

Reset wakeup

1 : RTC

RTC wakeup

2 : Digital

Digital input wakeup

End of enumeration elements list.

resetcause :
bits : 8 - 7 (0 bit)

Enumeration:

0 : PowerOn

Power-on reset

1 : External

External reset

2 : Watchdog

Watchdog reset

End of enumeration elements list.


pmusleep

PMU Sleep Register
address_offset : 0x148 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

pmusleep pmusleep write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sleep

sleep :
bits : 0 - -1 (0 bit)


pmukey

PMU Key Register
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmukey pmukey read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

pmuwakepm[0]

PMU Wake Program Memory
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmuwakepm[0] pmuwakepm[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmusleeppm[0]

PMU Sleep Program Memory
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmusleeppm[0] pmusleeppm[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmuwakepm[1]

PMU Wake Program Memory
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmuwakepm[1] pmuwakepm[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmusleeppm[1]

PMU Sleep Program Memory
address_offset : 0x364 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmusleeppm[1] pmusleeppm[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmuwakepm[2]

PMU Wake Program Memory
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmuwakepm[2] pmuwakepm[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmusleeppm[2]

PMU Sleep Program Memory
address_offset : 0x48C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmusleeppm[2] pmusleeppm[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmuwakepm[3]

PMU Wake Program Memory
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmuwakepm[3] pmuwakepm[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmusleeppm[3]

PMU Sleep Program Memory
address_offset : 0x5B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmusleeppm[3] pmusleeppm[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmuwakepm[4]

PMU Wake Program Memory
address_offset : 0x628 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmuwakepm[4] pmuwakepm[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmusleeppm[4]

PMU Sleep Program Memory
address_offset : 0x6E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmusleeppm[4] pmusleeppm[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmuwakepm[5]

PMU Wake Program Memory
address_offset : 0x73C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmuwakepm[5] pmuwakepm[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmusleeppm[5]

PMU Sleep Program Memory
address_offset : 0x81C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmusleeppm[5] pmusleeppm[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmuwakepm[6]

PMU Wake Program Memory
address_offset : 0x854 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmuwakepm[6] pmuwakepm[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmusleeppm[6]

PMU Sleep Program Memory
address_offset : 0x954 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmusleeppm[6] pmusleeppm[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmuwakepm[7]

PMU Wake Program Memory
address_offset : 0x970 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmuwakepm[7] pmuwakepm[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)


pmusleeppm[7]

PMU Sleep Program Memory
address_offset : 0xA90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pmusleeppm[7] pmusleeppm[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay pmu_out_0_en pmu_out_1_en corerst hfclkrst isolate

delay :
bits : 0 - -1 (0 bit)

pmu_out_0_en :
bits : 4 - 3 (0 bit)

pmu_out_1_en :
bits : 5 - 4 (0 bit)

corerst :
bits : 7 - 6 (0 bit)

hfclkrst :
bits : 8 - 7 (0 bit)

isolate :
bits : 9 - 8 (0 bit)



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