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PRCI

Peripheral Memory Blocks

Registers

hfrosccfg

coreclkcfg

hfxosccfg

pllcfg

plloutdiv


hfrosccfg

Clock Configuration Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

hfrosccfg hfrosccfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 div trim enable ready

div :
bits : 0 - -1 (0 bit)

trim :
bits : 16 - 15 (0 bit)

enable :
bits : 30 - 29 (0 bit)

ready :
bits : 31 - 30 (0 bit)


coreclkcfg

Clock Configuration Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

coreclkcfg coreclkcfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

hfxosccfg

Clock Configuration Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

hfxosccfg hfxosccfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enable ready

enable :
bits : 30 - 29 (0 bit)

ready :
bits : 31 - 30 (0 bit)


pllcfg

PLL Configuration Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pllcfg pllcfg read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pllr pllf pllq sel refsel bypass lock

pllr :
bits : 0 - -1 (0 bit)

Enumeration: PLLR

0 : R1

None

1 : R2

None

2 : R3

None

3 : R4

None

End of enumeration elements list.

pllf :
bits : 4 - 3 (0 bit)

pllq :
bits : 10 - 9 (0 bit)

Enumeration: PLLQ

1 : Q2

None

2 : Q4

None

3 : Q8

None

End of enumeration elements list.

sel :
bits : 16 - 15 (0 bit)

refsel :
bits : 17 - 16 (0 bit)

bypass :
bits : 18 - 17 (0 bit)

lock :
bits : 31 - 30 (0 bit)


plloutdiv

PLL Divider Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

plloutdiv plloutdiv read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 div divby1

div :
bits : 0 - -1 (0 bit)

divby1 :
bits : 8 - 7 (0 bit)



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