\n
Clock Configuration Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
div :
bits : 0 - -1 (0 bit)
trim :
bits : 16 - 15 (0 bit)
enable :
bits : 30 - 29 (0 bit)
ready :
bits : 31 - 30 (0 bit)
Clock Configuration Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Clock Configuration Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
enable :
bits : 30 - 29 (0 bit)
ready :
bits : 31 - 30 (0 bit)
PLL Configuration Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pllr :
bits : 0 - -1 (0 bit)
Enumeration: PLLR
0 : R1
None
1 : R2
None
2 : R3
None
3 : R4
None
End of enumeration elements list.
pllf :
bits : 4 - 3 (0 bit)
pllq :
bits : 10 - 9 (0 bit)
Enumeration: PLLQ
1 : Q2
None
2 : Q4
None
3 : Q8
None
End of enumeration elements list.
sel :
bits : 16 - 15 (0 bit)
refsel :
bits : 17 - 16 (0 bit)
bypass :
bits : 18 - 17 (0 bit)
lock :
bits : 31 - 30 (0 bit)
PLL Divider Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
div :
bits : 0 - -1 (0 bit)
divby1 :
bits : 8 - 7 (0 bit)
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