\n
Transmit Data Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data :
bits : 0 - -1 (0 bit)
full :
bits : 31 - 30 (0 bit)
Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txwm :
bits : 0 - -1 (0 bit)
rxwm :
bits : 1 - 0 (0 bit)
Interrupt Pending Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txwm :
bits : 0 - -1 (0 bit)
rxwm :
bits : 1 - 0 (0 bit)
Baud Rate Divisor Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value :
bits : 0 - -1 (0 bit)
Receive Data Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data :
bits : 0 - -1 (0 bit)
empty :
bits : 31 - 30 (0 bit)
Transmit Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
enable :
bits : 0 - -1 (0 bit)
nstop :
bits : 1 - 0 (0 bit)
counter :
bits : 16 - 15 (0 bit)
Receive Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
enable :
bits : 0 - -1 (0 bit)
counter :
bits : 16 - 15 (0 bit)
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