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QSPI

Peripheral Memory Blocks

Registers

div

csid

csdef

csmode

delay0

delay1

mode

fmt

txdata

rxdata

txmark

rxmark

fctrl

ffmt

ie

ip


div

Serial Clock Divisor Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

div div read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value :
bits : 0 - -1 (0 bit)


csid

Chip Select ID Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

csid csid read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

csdef

Chip Select Default Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

csdef csdef read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

csmode

Chip Select Mode Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

csmode csmode read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

delay0

Delay Control 0 Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

delay0 delay0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cssck sckcs

cssck :
bits : 0 - -1 (0 bit)

sckcs :
bits : 16 - 15 (0 bit)


delay1

Delay Control 1 Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

delay1 delay1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 intercs interxfr

intercs :
bits : 0 - -1 (0 bit)

interxfr :
bits : 16 - 15 (0 bit)


mode

Serial Clock Mode Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

mode mode read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 phase polarity

phase :
bits : 0 - -1 (0 bit)

polarity :
bits : 1 - 0 (0 bit)


fmt

Frame Format Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

fmt fmt read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 protocol endian direction length

protocol :
bits : 0 - -1 (0 bit)

Enumeration:

0 : Single

DQ0 (MOSI), DQ1 (MISO)

1 : Dual

DQ0, DQ1

2 : Quad

DQ0, DQ1, DQ2, DQ3

End of enumeration elements list.

endian :
bits : 2 - 1 (0 bit)

Enumeration:

0 : Big

Transmit MSB first.

1 : Little

Transmit LSB first.

End of enumeration elements list.

direction :
bits : 3 - 2 (0 bit)

Enumeration:

0 : Rx

For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal.

1 : Tx

The receive FIFO is not populated.

End of enumeration elements list.

length :
bits : 16 - 15 (0 bit)


txdata

Transmit Data Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

txdata txdata read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data full

data :
bits : 0 - -1 (0 bit)

full :
bits : 31 - 30 (0 bit)


rxdata

Receive Data Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rxdata rxdata read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data empty

data :
bits : 0 - -1 (0 bit)

empty :
bits : 31 - 30 (0 bit)


txmark

Transmit Watermark Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

txmark txmark read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value :
bits : 0 - -1 (0 bit)


rxmark

Receive Watermark Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rxmark rxmark read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value :
bits : 0 - -1 (0 bit)


fctrl

SPI Flash Interface Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

fctrl fctrl read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enable

enable :
bits : 0 - -1 (0 bit)


ffmt

SPI Flash Instruction Format Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ffmt ffmt read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pad_cnt cmd_en addr_len cmd_proto addr_proto data_proto cmd_code pad_code

pad_cnt : Number of dummy cycles
bits : 0 - -1 (0 bit)

cmd_en : Enable sending of command
bits : 0 - -1 (0 bit)

addr_len : Number of address bytes (0 to 4)
bits : 1 - 0 (0 bit)

cmd_proto : Protocol for transmitting command
bits : 8 - 7 (0 bit)

Enumeration:

0 : Single

DQ0 (MOSI), DQ1 (MISO)

1 : Dual

DQ0, DQ1

2 : Quad

DQ0, DQ1, DQ2, DQ3

End of enumeration elements list.

addr_proto : Protocol for transmitting address and padding
bits : 10 - 9 (0 bit)

Enumeration:

0 : Single

DQ0 (MOSI), DQ1 (MISO)

1 : Dual

DQ0, DQ1

2 : Quad

DQ0, DQ1, DQ2, DQ3

End of enumeration elements list.

data_proto : Protocol for receiving data bytes
bits : 12 - 11 (0 bit)

Enumeration:

0 : Single

DQ0 (MOSI), DQ1 (MISO)

1 : Dual

DQ0, DQ1

2 : Quad

DQ0, DQ1, DQ2, DQ3

End of enumeration elements list.

cmd_code : Value of command byte
bits : 16 - 15 (0 bit)

pad_code : First 8 bits to transmit during dummy cycles
bits : 24 - 23 (0 bit)


ie

SPI Interrupt Enable Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ie ie read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txwm rxwm

txwm :
bits : 0 - -1 (0 bit)

rxwm :
bits : 1 - 0 (0 bit)


ip

SPI Interrupt Pending Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ip ip read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txwm rxwm

txwm :
bits : 0 - -1 (0 bit)

rxwm :
bits : 1 - 0 (0 bit)



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