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Serial Clock Divisor Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value :
bits : 0 - -1 (0 bit)
Chip Select ID Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Chip Select Default Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Chip Select Mode Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Delay Control 0 Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
cssck :
bits : 0 - -1 (0 bit)
sckcs :
bits : 16 - 15 (0 bit)
Delay Control 1 Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
intercs :
bits : 0 - -1 (0 bit)
interxfr :
bits : 16 - 15 (0 bit)
Serial Clock Mode Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
phase :
bits : 0 - -1 (0 bit)
polarity :
bits : 1 - 0 (0 bit)
Frame Format Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
protocol :
bits : 0 - -1 (0 bit)
Enumeration:
0 : Single
DQ0 (MOSI), DQ1 (MISO)
1 : Dual
DQ0, DQ1
2 : Quad
DQ0, DQ1, DQ2, DQ3
End of enumeration elements list.
endian :
bits : 2 - 1 (0 bit)
Enumeration:
0 : Big
Transmit MSB first.
1 : Little
Transmit LSB first.
End of enumeration elements list.
direction :
bits : 3 - 2 (0 bit)
Enumeration:
0 : Rx
For dual and quad protocols, the DQ pins are tri-stated. For
the single protocol, the DQ0 pin is driven with the transmit
data as normal.
1 : Tx
The receive FIFO is not populated.
End of enumeration elements list.
length :
bits : 16 - 15 (0 bit)
Transmit Data Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data :
bits : 0 - -1 (0 bit)
full :
bits : 31 - 30 (0 bit)
Receive Data Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data :
bits : 0 - -1 (0 bit)
empty :
bits : 31 - 30 (0 bit)
Transmit Watermark Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value :
bits : 0 - -1 (0 bit)
Receive Watermark Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
value :
bits : 0 - -1 (0 bit)
SPI Flash Interface Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
enable :
bits : 0 - -1 (0 bit)
SPI Flash Instruction Format Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pad_cnt : Number of dummy cycles
bits : 0 - -1 (0 bit)
cmd_en : Enable sending of command
bits : 0 - -1 (0 bit)
addr_len : Number of address bytes (0 to 4)
bits : 1 - 0 (0 bit)
cmd_proto : Protocol for transmitting command
bits : 8 - 7 (0 bit)
Enumeration:
0 : Single
DQ0 (MOSI), DQ1 (MISO)
1 : Dual
DQ0, DQ1
2 : Quad
DQ0, DQ1, DQ2, DQ3
End of enumeration elements list.
addr_proto : Protocol for transmitting address and padding
bits : 10 - 9 (0 bit)
Enumeration:
0 : Single
DQ0 (MOSI), DQ1 (MISO)
1 : Dual
DQ0, DQ1
2 : Quad
DQ0, DQ1, DQ2, DQ3
End of enumeration elements list.
data_proto : Protocol for receiving data bytes
bits : 12 - 11 (0 bit)
Enumeration:
0 : Single
DQ0 (MOSI), DQ1 (MISO)
1 : Dual
DQ0, DQ1
2 : Quad
DQ0, DQ1, DQ2, DQ3
End of enumeration elements list.
cmd_code : Value of command byte
bits : 16 - 15 (0 bit)
pad_code : First 8 bits to transmit during dummy cycles
bits : 24 - 23 (0 bit)
SPI Interrupt Enable Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txwm :
bits : 0 - -1 (0 bit)
rxwm :
bits : 1 - 0 (0 bit)
SPI Interrupt Pending Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
txwm :
bits : 0 - -1 (0 bit)
rxwm :
bits : 1 - 0 (0 bit)
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