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I2C

Peripheral Memory Blocks

Registers

prer_lo

cr_sr

cr

sr

prer_hi

ctr

txr_rxr


prer_lo

Clock Prescale register lo-byte
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

prer_lo prer_lo read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value :
bits : 0 - 7 (8 bit)


cr_sr

Command register / Status register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

cr_sr cr_sr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

cr

Command register
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

cr cr write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 iack ack wr rd sto sta

iack : Interrupt acknowledge. When set, clears a pending interrupt
bits : 0 - 0 (1 bit)

ack : When a receiver, sent ACK (0) or NACK (1)
bits : 3 - 6 (4 bit)

Enumeration:

0 : ack

None

1 : nack

None

End of enumeration elements list.

wr : Write to slave
bits : 4 - 8 (5 bit)

rd : Read from slave
bits : 5 - 10 (6 bit)

sto : Generate stop condition
bits : 6 - 12 (7 bit)

sta : Generate (repeated) start condition
bits : 7 - 14 (8 bit)


sr

Status register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
alternate_register : cr
reset_Mask : 0x0

sr sr read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 if tip al busy rx_ack

if : Interrupt Flag. This bit is set when an interrupt is pending, which will cause a processor interrupt request if the IEN bit is set.
bits : 0 - 0 (1 bit)

tip : Transfer in progress
bits : 1 - 2 (2 bit)

al : Arbitration lost
bits : 5 - 10 (6 bit)

busy : I2C bus busy
bits : 6 - 12 (7 bit)

rx_ack : Received acknowledge from slave. This flag represents acknowledge from the addressed slave. '1' = No acknowledge received '0' = Acknowledge received
bits : 7 - 14 (8 bit)


prer_hi

Clock Prescale register hi-byte
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

prer_hi prer_hi read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value

value :
bits : 0 - 7 (8 bit)


ctr

Control register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ctr ctr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ien en

ien : I2C core interrupt enable bit
bits : 6 - 12 (7 bit)

en : I2C core enable bit
bits : 7 - 14 (8 bit)


txr_rxr

Transmit register / Receive register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

txr_rxr txr_rxr read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data :
bits : 0 - 7 (8 bit)



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