Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHBSEL : AHB Clock Source Select.
bits : 0 - 2 (3 bit)
Enumeration:
0 : LPOSC0
AHB clock source is the Low-Power Oscillator.
1 : LFOSC0
AHB clock source is the Low-Frequency Oscillator.
2 : RTC0OSC
AHB clock source is the RTC Oscillator.
3 : EXTOSC0
AHB clock source is the External Oscillator.
5 : PLL0OSC
AHB clock source is the PLL.
6 : LPOSC0_DIV
AHB clock source is a divided version of the Low-Power Oscillator.
End of enumeration elements list.
AHBDIV : AHB Clock Divider.
bits : 8 - 10 (3 bit)
Enumeration:
0 : DIV1
AHB clock divided by 1.
1 : DIV2
AHB clock divided by 2.
2 : DIV4
AHB clock divided by 4.
3 : DIV8
AHB clock divided by 8.
4 : DIV16
AHB clock divided by 16.
5 : DIV32
AHB clock divided by 32.
6 : DIV64
AHB clock divided by 64.
7 : DIV128
AHB clock divided by 128.
End of enumeration elements list.
APBDIV : APB Clock Divider.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DIV1
APB clock is the same as the AHB clock (divided by 1).
1 : DIV2
APB clock is the AHB clock divided by 2.
End of enumeration elements list.
EXTESEL : External Clock Edge Select.
bits : 28 - 28 (1 bit)
Enumeration:
0 : BOTH_EDGES
External clock generated by both rising and falling edges of the external oscillator.
1 : RISING_ONLY
External clock generated by only rising edges of the external oscillator.
End of enumeration elements list.
OBUSYF : Oscillators Busy Flag.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
AHB and APB oscillators are not busy.
1 : SET
AHB and APB oscillators are busy and the AHBSEL, AHBDIV, and APBDIV fields should not be modified.
End of enumeration elements list.
AHB Clock Gate
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMCEN : RAM Clock Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the AHB clock to the RAM.
1 : ENABLED
Enable the AHB clock to the RAM (default).
End of enumeration elements list.
DMACEN : DMA Controller Clock Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable the AHB clock to the DMA Controller (default).
1 : ENABLED
Enable the AHB clock to the DMA Controller.
End of enumeration elements list.
FLASHCEN : Flash Clock Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable the AHB clock to the Flash.
1 : ENABLED
Enable the AHB clock to the Flash (default).
End of enumeration elements list.
EMIF0CEN : EMIF Clock Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
Disable the AHB clock to the External Memory Interface (EMIF) (default).
1 : ENABLED
Enable the AHB clock to the External Memory Interface (EMIF).
End of enumeration elements list.
APB Clock Gate 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL0CEN : PLL Module Clock Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the PLL0 registers (default).
1 : ENABLED
Enable the APB clock to the PLL0 registers.
End of enumeration elements list.
PB0CEN : Port Bank Module Clock Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the Port Bank Modules (default).
1 : ENABLED
Enable the APB clock to the Port Bank Modules.
End of enumeration elements list.
USART0CEN : USART0 Module Clock Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the USART0 Module (default).
1 : ENABLED
Enable the APB clock to the USART0 Module.
End of enumeration elements list.
USART1CEN : USART1 Module Clock Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the USART1 Module (default).
1 : ENABLED
Enable the APB clock to the USART1 Module.
End of enumeration elements list.
UART0CEN : UART0 Module Clock Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the UART0 Module (default).
1 : ENABLED
Enable the APB clock to the UART0 Module.
End of enumeration elements list.
UART1CEN : UART1 Module Clock Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the UART1 Module (default).
1 : ENABLED
Enable the APB clock to the UART1 Module.
End of enumeration elements list.
SPI0CEN : SPI0 Module Clock Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the SPI0 Module (default).
1 : ENABLED
Enable the APB clock to the SPI0 Module.
End of enumeration elements list.
SPI1CEN : SPI1 Module Clock Enable.
bits : 7 - 7 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the SPI1 Module (default).
1 : ENABLED
Enable the APB clock to the SPI1 Module.
End of enumeration elements list.
SPI2CEN : SPI2 Module Clock Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the SPI2 Module (default).
1 : ENABLED
Enable the APB clock to the SPI2 Module.
End of enumeration elements list.
I2C0CEN : I2C0 Module Clock Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the I2C0 Module (default).
1 : ENABLED
Enable the APB clock to the I2C0 Module.
End of enumeration elements list.
I2C1CEN : I2C1 Module Clock Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the I2C1 Module (default).
1 : ENABLED
Enable the APB clock to the I2C1 Module.
End of enumeration elements list.
EPCA0CEN : EPCA0 Module Clock Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the EPCA0 Module (default).
1 : ENABLED
Enable the APB clock to the EPCA0 Module.
End of enumeration elements list.
PCA0CEN : PCA0 Module Clock Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the PCA0 Module (default).
1 : ENABLED
Enable the APB clock to the PCA0 Module.
End of enumeration elements list.
PCA1CEN : PCA1 Module Clock Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the PCA1 Module (default).
1 : ENABLED
Enable the APB clock to the PCA1 Module.
End of enumeration elements list.
SSG0CEN : SSG0 Module Clock Enable.
bits : 14 - 14 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the SSG0 Module (default).
1 : ENABLED
Enable the APB clock to the SSG0 Module.
End of enumeration elements list.
TIMER0CEN : TIMER0 Module Clock Enable.
bits : 15 - 15 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the TIMER0 Module (default).
1 : ENABLED
Enable the APB clock to the TIMER0 Module.
End of enumeration elements list.
TIMER1CEN : TIMER1 Module Clock Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the TIMER1 Module (default).
1 : ENABLED
Enable the APB clock to the TIMER1 Module.
End of enumeration elements list.
ADC0CEN : SARADC0 Module Clock Enable.
bits : 17 - 17 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the SARADC0 Module (default).
1 : ENABLED
Enable the APB clock to the SARADC0 Module.
End of enumeration elements list.
ADC1CEN : SARADC1 Module Clock Enable.
bits : 18 - 18 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the SARADC1 Module (default).
1 : ENABLED
Enable the APB clock to the SARADC1 Module.
End of enumeration elements list.
CMP0CEN : Comparator 0 Module Clock Enable.
bits : 19 - 19 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the Comparator 0 Module (default).
1 : ENABLED
Enable the APB clock to the Comparator 0 Module.
End of enumeration elements list.
CMP1CEN : Comparator 1 Module Clock Enable.
bits : 20 - 20 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the Comparator 1 Module (default).
1 : ENABLED
Enable the APB clock to the Comparator 1 Module.
End of enumeration elements list.
CS0CEN : Capacitive Sensing (CAPSENSE0) Module Clock Enable.
bits : 21 - 21 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the CAPSENSE0 Module (default).
1 : ENABLED
Enable the APB clock to the CAPSENSE0 Module.
End of enumeration elements list.
AES0CEN : AES0 Module Clock Enable.
bits : 22 - 22 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the AES0 Module (default).
1 : ENABLED
Enable the APB clock to the AES0 Module.
End of enumeration elements list.
CRC0CEN : CRC0 Module Clock Enable.
bits : 23 - 23 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the CRC0 Module (default).
1 : ENABLED
Enable the APB clock to the CRC0 Module.
End of enumeration elements list.
IDAC0CEN : IDAC0 Module Clock Enable.
bits : 24 - 24 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the IDAC0 Module (default).
1 : ENABLED
Enable the APB clock to the IDAC0 Module.
End of enumeration elements list.
IDAC1CEN : IDAC1 Module Clock Enable.
bits : 25 - 25 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the IDAC1 Module (default).
1 : ENABLED
Enable the APB clock to the IDAC1 Module.
End of enumeration elements list.
LPT0CEN : Low Power Timer (LPTIMER0) Module Clock Enable.
bits : 26 - 26 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the LPTIMER0 Module (default).
1 : ENABLED
Enable the APB clock to the LPTIMER0 Module.
End of enumeration elements list.
I2S0CEN : I2S0 Module Clock Enable.
bits : 27 - 27 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the I2S0 Module (default).
1 : ENABLED
Enable the APB clock to the I2S0 Module.
End of enumeration elements list.
EVREGCEN : External Regulator Clock Enable.
bits : 29 - 29 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the External Regulator Module (EXTVREG0) (default).
1 : ENABLED
Enable the APB clock to the External Regulator Module (EXTVREG0).
End of enumeration elements list.
FLCTRLCEN : Flash Controller Clock Enable.
bits : 30 - 30 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the Flash Controller Module (FLASHCTRL0) (default).
1 : ENABLED
Enable the APB clock to the Flash Controller Module (FLASHCTRL0).
End of enumeration elements list.
APB Clock Gate 1
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MISC0CEN : Miscellaneous 0 Clock Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, LPOSC0, EXTVREG0, IVC0 and RTC0 modules (default).
1 : ENABLED
Enable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, LPOSC0, EXTVREG0, IVC0 and RTC0 modules.
End of enumeration elements list.
MISC1CEN : Miscellaneous 1 Clock Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar (DMAXBAR0) modules.
1 : ENABLED
Enable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar (DMAXBAR0) modules (default).
End of enumeration elements list.
MISC2CEN : Miscellaneous 2 Clock Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the OSCVLDF flag in the EXTOSC module (default).
1 : ENABLED
Enable the APB clock to the OSCVLDF flag in the EXTOSC module.
End of enumeration elements list.
Power Mode 3 Clock Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PM3CSEL : Power Mode 3 Fast-Wake Clock Source.
bits : 0 - 2 (3 bit)
Enumeration:
0 : LPOSC0
Power Mode 3 clock source is the Low-Power Oscillator.
1 : LFOSC0
Power Mode 3 clock source is the Low-Frequency Oscillator.
2 : RTC0OSC
Power Mode 3 clock source is the RTC Oscillator.
3 : EXTOSC0
Power Mode 3 clock source is the External Oscillator.
5 : PLL0OSC
Power Mode 3 clock source is the PLL.
6 : LPOSC0_DIV
Power Mode 3 clock source is a divided version of the Low-Power Oscillator.
End of enumeration elements list.
PM3CEN : Power Mode 3 Fast-Wake Clock Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
Disable the core clock when in Power Mode 3.
1 : ENABLED
The core clock is enabled and runs off the clock selected by PM3CSEL in Power Mode 3.
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.