Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPSEL : Sampling Phase Select.
bits : 0 - 3 (4 bit)
Enumeration:
0 : PHASE0
The ADC samples at SSG phase 0.
1 : PHASE1
The ADC samples at SSG phase 1.
2 : PHASE2
The ADC samples at SSG phase 2.
3 : PHASE3
The ADC samples at SSG phase 3.
4 : PHASE4
The ADC samples at SSG phase 4.
5 : PHASE5
The ADC samples at SSG phase 5.
6 : PHASE6
The ADC samples at SSG phase 6.
7 : PHASE7
The ADC samples at SSG phase 7.
8 : PHASE8
The ADC samples at SSG phase 8.
9 : PHASE9
The ADC samples at SSG phase 9.
10 : PHASE10
The ADC samples at SSG phase 10.
11 : PHASE11
The ADC samples at SSG phase 11.
12 : PHASE12
The ADC samples at SSG phase 12.
13 : PHASE13
The ADC samples at SSG phase 13.
14 : PHASE14
The ADC samples at SSG phase 14.
15 : PHASE15
The ADC samples at SSG phase 15.
End of enumeration elements list.
SPEN : Sampling Phase Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
Disable Phase Select. The ADC will always sample on the start-of-conversion trigger selected by the SCSEL field.
1 : ENABLED
Enable Phase Select. The ADC will sample according to the phase selected by the SPSEL field.
End of enumeration elements list.
SSGEN : Synchronous Sample Generator Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DISABLED
Disable the SAR clock output to SSG.
1 : ENABLED
The ADC is the SSG master, and the SAR clock will be output to the SSG block.
End of enumeration elements list.
PACKMD : Output Packing Mode.
bits : 6 - 7 (2 bit)
Enumeration:
0 : UPPER_ONLY
Data is written to the upper half-word and the lower half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled.
1 : LOWER_ONLY
Data is written to the lower half-word, and the upper half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled.
2 : UPPER_FIRST
Two data words are packed into the register with the upper half-word representing the earlier data, and the lower half-word representing the later data. If SIMCEN is set to 1, the upper half-word represents data from the master ADC (selected by SSGEN) and the lower half-word represents data from the slave ADC. The ADC write to the lower half-word will trigger the SCI interrupt, if enabled.
3 : LOWER_FIRST
Two data words are packed into the register with the lower half-word representing the earlier data, and the upper half-word representing the later data. If SIMCEN is set to 1, the lower half-word represents data from the master ADC (selected by SSGEN) and the upper half-word represents data from the slave ADC. The ADC write to the upper half-word will trigger the SCI interrupt, if enabled.
End of enumeration elements list.
SIMCEN : Simultaneous Conversion Packing Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable simultaneous mode conversion packing.
1 : ENABLED
Enable simultaneous mode conversion packing.
End of enumeration elements list.
INTLVEN : Interleaved Conversion Packing Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Disable interleaved mode conversion packing.
1 : ENABLED
Enable interleaved mode conversion packing.
End of enumeration elements list.
SCANEN : Scan Mode Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Disable ADC scan mode.
1 : ENABLED
Enable ADC scan mode. The ADC will scan through the defined time slots in sequence on every start of conversion.
End of enumeration elements list.
SCANMD : Scan Mode Select.
bits : 12 - 12 (1 bit)
Enumeration:
0 : ONCE
The channel sequencer will cycle through all of the specified time slots once.
1 : LOOP
The channel sequencer will cycle through all of the specified time slots in a loop until SCANEN is cleared to 0.
End of enumeration elements list.
DMAEN : DMA Interface Enable .
bits : 14 - 14 (1 bit)
Enumeration:
0 : DISABLED
Disable the ADC module DMA interface.
1 : ENABLED
Enable the ADC module DMA interface.
End of enumeration elements list.
BCLKSEL : Burst Mode Clock Select.
bits : 15 - 15 (1 bit)
Enumeration:
0 : LPOSC0
Burst mode uses the Low Power Oscillator.
1 : APB
Burst mode uses the APB clock.
End of enumeration elements list.
CLKDIV : SAR Clock Divider.
bits : 16 - 26 (11 bit)
SCCIEN : Single Conversion Complete Interrupt Enable.
bits : 27 - 27 (1 bit)
Enumeration:
0 : DISABLED
Disable the ADC single data conversion complete interrupt.
1 : ENABLED
Enable the ADC single data conversion complete interrupt.
End of enumeration elements list.
SDIEN : Scan Done Interrupt Enable.
bits : 28 - 28 (1 bit)
Enumeration:
0 : DISABLED
Disable the ADC scan complete interrupt.
1 : ENABLED
Enable the ADC scan complete interrupt.
End of enumeration elements list.
FORIEN : FIFO Overrun Interrupt Enable.
bits : 29 - 29 (1 bit)
Enumeration:
0 : DISABLED
Disable the data FIFO overrun interrupt.
1 : ENABLED
Enable the data FIFO overrun interrupt.
End of enumeration elements list.
FURIEN : FIFO Underrun Interrupt Enable.
bits : 30 - 30 (1 bit)
Enumeration:
0 : DISABLED
Disable the data FIFO underrun interrupt.
1 : ENABLED
Enable the data FIFO underrun interrupt.
End of enumeration elements list.
Measurement Control
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFGNDSEL : Reference Ground Select.
bits : 0 - 0 (1 bit)
Enumeration:
0 : INTERNAL
The internal device ground is used as the ground reference for ADC conversions.
1 : EXTERNAL
The VREFGND pin is used as the ground reference for ADC conversions.
End of enumeration elements list.
CLKESEL : Sampling Clock Edge Select.
bits : 1 - 1 (1 bit)
Enumeration:
0 : RISING
Select the rising edge of the APB clock.
1 : FALLING
Select the falling edge of the APB clock.
End of enumeration elements list.
BMTK : Burst Mode Tracking Time.
bits : 2 - 7 (6 bit)
SCSEL : Start-Of-Conversion Source Select.
bits : 8 - 11 (4 bit)
Enumeration:
0 : ADCNT0
An ADC conversion triggers from the ADCnT0 ("On Demand" by writing 1 to ADBUSY) trigger source.
1 : ADCNT1
An ADC conversion triggers from the ADCnT1 (Timer 0 Low Overflow) trigger source.
2 : ADCNT2
An ADC conversion triggers from the ADCnT2 (Timer 0 High Overflow) trigger source.
3 : ADCNT3
An ADC conversion triggers from the ADCnT3 (Timer 1 Low Overflow) trigger source.
4 : ADCNT4
An ADC conversion triggers from the ADCnT4 (Timer 1 High Overflow) trigger source.
5 : ADCNT5
An ADC conversion triggers from the ADCnT5 (EPCA0 synchronization pulse) trigger source.
6 : ADCNT6
An ADC conversion triggers from the ADCnT6 (I2C0 Timer overflow) trigger source.
7 : ADCNT7
An ADC conversion triggers from the ADCnT7 (I2C1 Timer overflow) trigger source.
8 : ADCNT8
An ADC conversion triggers from the ADCnT8 (SSG phase defined by ADSP bits) trigger source.
9 : ADCNT9
An ADC conversion triggers from the ADCnT9 (RESERVED) trigger source.
10 : ADCNT10
An ADC conversion triggers from the ADCnT10 (RESERVED) trigger source.
11 : ADCNT11
An ADC conversion triggers from the ADCnT11 (RESERVED) trigger source.
12 : ADCNT12
An ADC conversion triggers from the ADCnT12 (RESERVED) trigger source.
13 : ADCNT13
An ADC conversion triggers from the ADCnT13 (RESERVED) trigger source.
14 : ADCNT14
An ADC conversion triggers from the ADCnT14 (RESERVED) trigger source.
15 : ADCNT15
An ADC conversion triggers from the ADCnT15 (PB1.6) trigger source.
End of enumeration elements list.
PWRTIME : Burst Mode Power Up Time.
bits : 12 - 15 (4 bit)
BURSTEN : Burst Mode Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
Disable burst mode.
1 : ENABLED
Enable burst mode.
End of enumeration elements list.
ADCEN : ADC Enable.
bits : 17 - 17 (1 bit)
Enumeration:
0 : DISABLED
Disable the ADC (low-power shutdown).
1 : ENABLED
Enable the ADC (active and ready for data conversions).
End of enumeration elements list.
AD12BSSEL : 12-Bit Mode Sample Select.
bits : 18 - 18 (1 bit)
Enumeration:
0 : FOUR
The ADC re-samples the input before each of the four conversions.
1 : ONE
The ADC samples once before the first conversion and converts four times.
End of enumeration elements list.
VCMEN : Common Mode Buffer Enable.
bits : 19 - 19 (1 bit)
Enumeration:
0 : DISABLED
Disable the common mode buffer.
1 : ENABLED
Enable the common mode buffer.
End of enumeration elements list.
ACCMD : Accumulation Mode.
bits : 21 - 21 (1 bit)
Enumeration:
0 : ACCUMULATE
Conversions will be accumulated for the specified number of cycles in burst mode according to the channel configuration.
1 : REPEAT
Conversions will not be accumulated in burst mode.
End of enumeration elements list.
TRKMD : ADC Tracking Mode.
bits : 22 - 22 (1 bit)
Enumeration:
0 : NORMAL
Normal Tracking Mode: When the ADC is enabled, a conversion begins immediately following the start-of-conversion signal.
1 : DELAYED
Delayed Tracking Mode: When the ADC is enabled, a conversion begins 3 SAR clock cycles following the start-of-conversion signal. The ADC is allowed to track during this time.
End of enumeration elements list.
ADBUSY : ADC Busy.
bits : 23 - 23 (1 bit)
BIASSEL : Bias Power Select.
bits : 24 - 25 (2 bit)
Enumeration:
0 : MODE0
Select bias current mode 0. Recommended to use modes 1, 2, or 3.
1 : MODE1
Select bias current mode 1 (SARCLK = 16 MHz).
2 : MODE2
Select bias current mode 2.
3 : MODE3
Select bias current mode 3 (SARCLK = 4 MHz).
End of enumeration elements list.
LPMDEN : Low Power Mode Enable.
bits : 26 - 26 (1 bit)
Enumeration:
0 : DISABLED
Disable low power mode.
1 : ENABLED
Enable low power mode (requires extended tracking time).
End of enumeration elements list.
MREFLPEN : MUX and VREF Low Power Enable.
bits : 27 - 27 (1 bit)
Enumeration:
0 : DISABLED
Disable low power mode.
1 : ENABLED
Enable low power mode (SAR clock <= 4 MHz).
End of enumeration elements list.
VREFSEL : Voltage Reference Select.
bits : 30 - 31 (2 bit)
Enumeration:
0 : INTERNAL_VREF
Select the internal, dedicated SARADC voltage reference as the ADC reference.
1 : VDD
Select the VDD pin as the ADC reference.
2 : LDO_OUT
Select the output of the internal LDO regulator (~1.8 V) as the ADC reference.
3 : EXTERNAL_VREF
Select the VREF pin as the ADC reference. This option is used for either an external VREF or the on-chip VREF driving out to the VREF pin.
End of enumeration elements list.
Channel Sequencer Time Slots 4-7 Setup
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS4CHR : Time Slot 4 Conversion Characteristic.
bits : 0 - 1 (2 bit)
Enumeration:
0 : CC0
Select conversion characteristic 0 for time slot 4.
1 : CC1
Select conversion characteristic 1 for time slot 4.
2 : CC2
Select conversion characteristic 2 for time slot 4.
3 : CC3
Select conversion characteristic 3 for time slot 4.
End of enumeration elements list.
TS4MUX : Time Slot 4 Input Channel.
bits : 2 - 6 (5 bit)
Enumeration:
0 : ADCN0
Select channel ADCn.0 (RESERVED).
1 : ADCN1
Select channel ADCn.1 (RESERVED).
2 : ADCN2
Select channel ADCn.2 (PB0.0).
3 : ADCN3
Select channel ADCn.3 (PB0.1).
4 : ADCN4
Select channel ADCn.4 (PB0.2).
5 : ADCN5
Select channel ADCn.5 (PB0.3).
6 : ADCN6
Select channel ADCn.6 (PB0.4).
7 : ADCN7
Select channel ADCn.7 (PB0.5).
8 : ADCN8
Select channel ADCn.8 (PB0.6).
9 : ADCN9
Select channel ADCn.9 (PB0.8).
10 : ADCN10
Select channel ADCn.10 (PB0.9).
11 : ADCN11
Select channel ADCn.11 (RESERVED).
12 : ADCN12
Select channel ADCn.12 (PB0.14).
13 : ADCN13
Select channel ADCn.13 (PB0.15).
14 : ADCN14
Select channel ADCn.14 (PB1.0).
15 : ADCN15
Select channel ADCn.15 (PB1.1).
16 : ADCN16
Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).
17 : ADCN17
Select channel ADCn.17 (VSS).
18 : ADCN18
Select channel ADCn.18 (1.8V Output of LDO).
19 : ADCN19
Select channel ADCn.19 (VDD).
20 : ADCN20
Select channel ADCn.20 (Temperature Sensor Output).
21 : ADCN21
Select channel ADCn.21 (VIOHD / 4).
22 : ADCN22
Select channel ADCn.22 (RESERVED).
23 : ADCN23
Select channel ADCn.23 (RESERVED).
24 : ADCN24
Select channel ADCn.24 (RESERVED).
25 : ADCN25
Select channel ADCn.25 (RESERVED).
26 : ADCN26
Select channel ADCn.26 (RESERVED).
27 : ADCN27
Select channel ADCn.27 (RESERVED).
28 : ADCN28
Select channel ADCn.28 (RESERVED).
29 : ADCN29
Select channel ADCn.29 (RESERVED).
30 : ADCN30
Select channel ADCn.30 (RESERVED).
31 : END
None - End the sequence.
End of enumeration elements list.
TS5CHR : Time Slot 5 Conversion Characteristic.
bits : 8 - 9 (2 bit)
Enumeration:
0 : CC0
Select conversion characteristic 0 for time slot 5.
1 : CC1
Select conversion characteristic 1 for time slot 5.
2 : CC2
Select conversion characteristic 2 for time slot 5.
3 : CC3
Select conversion characteristic 3 for time slot 5.
End of enumeration elements list.
TS5MUX : Time Slot 5 Input Channel.
bits : 10 - 14 (5 bit)
Enumeration:
0 : ADCN0
Select channel ADCn.0 (RESERVED).
1 : ADCN1
Select channel ADCn.1 (RESERVED).
2 : ADCN2
Select channel ADCn.2 (PB0.0).
3 : ADCN3
Select channel ADCn.3 (PB0.1).
4 : ADCN4
Select channel ADCn.4 (PB0.2).
5 : ADCN5
Select channel ADCn.5 (PB0.3).
6 : ADCN6
Select channel ADCn.6 (PB0.4).
7 : ADCN7
Select channel ADCn.7 (PB0.5).
8 : ADCN8
Select channel ADCn.8 (PB0.6).
9 : ADCN9
Select channel ADCn.9 (PB0.8).
10 : ADCN10
Select channel ADCn.10 (PB0.9).
11 : ADCN11
Select channel ADCn.11 (RESERVED).
12 : ADCN12
Select channel ADCn.12 (PB0.14).
13 : ADCN13
Select channel ADCn.13 (PB0.15).
14 : ADCN14
Select channel ADCn.14 (PB1.0).
15 : ADCN15
Select channel ADCn.15 (PB1.1).
16 : ADCN16
Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).
17 : ADCN17
Select channel ADCn.17 (VSS).
18 : ADCN18
Select channel ADCn.18 (1.8V Output of LDO).
19 : ADCN19
Select channel ADCn.19 (VDD).
20 : ADCN20
Select channel ADCn.20 (Temperature Sensor Output).
21 : ADCN21
Select channel ADCn.21 (VIOHD / 4).
22 : ADCN22
Select channel ADCn.22 (RESERVED).
23 : ADCN23
Select channel ADCn.23 (RESERVED).
24 : ADCN24
Select channel ADCn.24 (RESERVED).
25 : ADCN25
Select channel ADCn.25 (RESERVED).
26 : ADCN26
Select channel ADCn.26 (RESERVED).
27 : ADCN27
Select channel ADCn.27 (RESERVED).
28 : ADCN28
Select channel ADCn.28 (RESERVED).
29 : ADCN29
Select channel ADCn.29 (RESERVED).
30 : ADCN30
Select channel ADCn.30 (RESERVED).
31 : END
None - End the sequence.
End of enumeration elements list.
TS6CHR : Time Slot 6 Conversion Characteristic.
bits : 16 - 17 (2 bit)
Enumeration:
0 : CC0
Select conversion characteristic 0 for time slot 6.
1 : CC1
Select conversion characteristic 1 for time slot 6.
2 : CC2
Select conversion characteristic 2 for time slot 6.
3 : CC3
Select conversion characteristic 3 for time slot 6.
End of enumeration elements list.
TS6MUX : Time Slot 6 Input Channel.
bits : 18 - 22 (5 bit)
Enumeration:
0 : ADCN0
Select channel ADCn.0 (RESERVED).
1 : ADCN1
Select channel ADCn.1 (RESERVED).
2 : ADCN2
Select channel ADCn.2 (PB0.0).
3 : ADCN3
Select channel ADCn.3 (PB0.1).
4 : ADCN4
Select channel ADCn.4 (PB0.2).
5 : ADCN5
Select channel ADCn.5 (PB0.3).
6 : ADCN6
Select channel ADCn.6 (PB0.4).
7 : ADCN7
Select channel ADCn.7 (PB0.5).
8 : ADCN8
Select channel ADCn.8 (PB0.6).
9 : ADCN9
Select channel ADCn.9 (PB0.8).
10 : ADCN10
Select channel ADCn.10 (PB0.9).
11 : ADCN11
Select channel ADCn.11 (RESERVED).
12 : ADCN12
Select channel ADCn.12 (PB0.14).
13 : ADCN13
Select channel ADCn.13 (PB0.15).
14 : ADCN14
Select channel ADCn.14 (PB1.0).
15 : ADCN15
Select channel ADCn.15 (PB1.1).
16 : ADCN16
Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).
17 : ADCN17
Select channel ADCn.17 (VSS).
18 : ADCN18
Select channel ADCn.18 (1.8V Output of LDO).
19 : ADCN19
Select channel ADCn.19 (VDD).
20 : ADCN20
Select channel ADCn.20 (Temperature Sensor Output).
21 : ADCN21
Select channel ADCn.21 (VIOHD / 4).
22 : ADCN22
Select channel ADCn.22 (RESERVED).
23 : ADCN23
Select channel ADCn.23 (RESERVED).
24 : ADCN24
Select channel ADCn.24 (RESERVED).
25 : ADCN25
Select channel ADCn.25 (RESERVED).
26 : ADCN26
Select channel ADCn.26 (RESERVED).
27 : ADCN27
Select channel ADCn.27 (RESERVED).
28 : ADCN28
Select channel ADCn.28 (RESERVED).
29 : ADCN29
Select channel ADCn.29 (RESERVED).
30 : ADCN30
Select channel ADCn.30 (RESERVED).
31 : END
None - End the sequence.
End of enumeration elements list.
TS7CHR : Time Slot 7 Conversion Characteristic.
bits : 24 - 25 (2 bit)
Enumeration:
0 : CC0
Select conversion characteristic 0 for time slot 7.
1 : CC1
Select conversion characteristic 1 for time slot 7.
2 : CC2
Select conversion characteristic 2 for time slot 7.
3 : CC3
Select conversion characteristic 3 for time slot 7.
End of enumeration elements list.
TS7MUX : Time Slot 7 Input Channel.
bits : 26 - 30 (5 bit)
Enumeration:
0 : ADCN0
Select channel ADCn.0 (RESERVED).
1 : ADCN1
Select channel ADCn.1 (RESERVED).
2 : ADCN2
Select channel ADCn.2 (PB0.0).
3 : ADCN3
Select channel ADCn.3 (PB0.1).
4 : ADCN4
Select channel ADCn.4 (PB0.2).
5 : ADCN5
Select channel ADCn.5 (PB0.3).
6 : ADCN6
Select channel ADCn.6 (PB0.4).
7 : ADCN7
Select channel ADCn.7 (PB0.5).
8 : ADCN8
Select channel ADCn.8 (PB0.6).
9 : ADCN9
Select channel ADCn.9 (PB0.8).
10 : ADCN10
Select channel ADCn.10 (PB0.9).
11 : ADCN11
Select channel ADCn.11 (RESERVED).
12 : ADCN12
Select channel ADCn.12 (PB0.14).
13 : ADCN13
Select channel ADCn.13 (PB0.15).
14 : ADCN14
Select channel ADCn.14 (PB1.0).
15 : ADCN15
Select channel ADCn.15 (PB1.1).
16 : ADCN16
Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).
17 : ADCN17
Select channel ADCn.17 (VSS).
18 : ADCN18
Select channel ADCn.18 (1.8V Output of LDO).
19 : ADCN19
Select channel ADCn.19 (VDD).
20 : ADCN20
Select channel ADCn.20 (Temperature Sensor Output).
21 : ADCN21
Select channel ADCn.21 (VIOHD / 4).
22 : ADCN22
Select channel ADCn.22 (RESERVED).
23 : ADCN23
Select channel ADCn.23 (RESERVED).
24 : ADCN24
Select channel ADCn.24 (RESERVED).
25 : ADCN25
Select channel ADCn.25 (RESERVED).
26 : ADCN26
Select channel ADCn.26 (RESERVED).
27 : ADCN27
Select channel ADCn.27 (RESERVED).
28 : ADCN28
Select channel ADCn.28 (RESERVED).
29 : ADCN29
Select channel ADCn.29 (RESERVED).
30 : ADCN30
Select channel ADCn.30 (RESERVED).
31 : END
None - End the sequence.
End of enumeration elements list.
Channel Sequencer Time Slots 0-3 Setup
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS0CHR : Time Slot 0 Conversion Characteristic.
bits : 0 - 1 (2 bit)
Enumeration:
0 : CC0
Select conversion characteristic 0 for time slot 0.
1 : CC1
Select conversion characteristic 1 for time slot 0.
2 : CC2
Select conversion characteristic 2 for time slot 0.
3 : CC3
Select conversion characteristic 3 for time slot 0.
End of enumeration elements list.
TS0MUX : Time Slot 0 Input Channel.
bits : 2 - 6 (5 bit)
Enumeration:
0 : ADCN0
Select channel ADCn.0 (RESERVED).
1 : ADCN1
Select channel ADCn.1 (RESERVED).
2 : ADCN2
Select channel ADCn.2 (PB0.0).
3 : ADCN3
Select channel ADCn.3 (PB0.1).
4 : ADCN4
Select channel ADCn.4 (PB0.2).
5 : ADCN5
Select channel ADCn.5 (PB0.3).
6 : ADCN6
Select channel ADCn.6 (PB0.4).
7 : ADCN7
Select channel ADCn.7 (PB0.5).
8 : ADCN8
Select channel ADCn.8 (PB0.6).
9 : ADCN9
Select channel ADCn.9 (PB0.8).
10 : ADCN10
Select channel ADCn.10 (PB0.9).
11 : ADCN11
Select channel ADCn.11 (RESERVED).
12 : ADCN12
Select channel ADCn.12 (PB0.14).
13 : ADCN13
Select channel ADCn.13 (PB0.15).
14 : ADCN14
Select channel ADCn.14 (PB1.0).
15 : ADCN15
Select channel ADCn.15 (PB1.1).
16 : ADCN16
Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).
17 : ADCN17
Select channel ADCn.17 (VSS).
18 : ADCN18
Select channel ADCn.18 (1.8V Output of LDO).
19 : ADCN19
Select channel ADCn.19 (VDD).
20 : ADCN20
Select channel ADCn.20 (Temperature Sensor Output).
21 : ADCN21
Select channel ADCn.21 (VIOHD / 4).
22 : ADCN22
Select channel ADCn.22 (RESERVED).
23 : ADCN23
Select channel ADCn.23 (RESERVED).
24 : ADCN24
Select channel ADCn.24 (RESERVED).
25 : ADCN25
Select channel ADCn.25 (RESERVED).
26 : ADCN26
Select channel ADCn.26 (RESERVED).
27 : ADCN27
Select channel ADCn.27 (RESERVED).
28 : ADCN28
Select channel ADCn.28 (RESERVED).
29 : ADCN29
Select channel ADCn.29 (RESERVED).
30 : ADCN30
Select channel ADCn.30 (RESERVED).
31 : END
None - End the sequence.
End of enumeration elements list.
TS1CHR : Time Slot 1 Conversion Characteristic.
bits : 8 - 9 (2 bit)
Enumeration:
0 : CC0
Select conversion characteristic 0 for time slot 1.
1 : CC1
Select conversion characteristic 1 for time slot 1.
2 : CC2
Select conversion characteristic 2 for time slot 1.
3 : CC3
Select conversion characteristic 3 for time slot 1.
End of enumeration elements list.
TS1MUX : Time Slot 1 Input Channel.
bits : 10 - 14 (5 bit)
Enumeration:
0 : ADCN0
Select channel ADCn.0 (RESERVED).
1 : ADCN1
Select channel ADCn.1 (RESERVED).
2 : ADCN2
Select channel ADCn.2 (PB0.0).
3 : ADCN3
Select channel ADCn.3 (PB0.1).
4 : ADCN4
Select channel ADCn.4 (PB0.2).
5 : ADCN5
Select channel ADCn.5 (PB0.3).
6 : ADCN6
Select channel ADCn.6 (PB0.4).
7 : ADCN7
Select channel ADCn.7 (PB0.5).
8 : ADCN8
Select channel ADCn.8 (PB0.6).
9 : ADCN9
Select channel ADCn.9 (PB0.8).
10 : ADCN10
Select channel ADCn.10 (PB0.9).
11 : ADCN11
Select channel ADCn.11 (RESERVED).
12 : ADCN12
Select channel ADCn.12 (PB0.14).
13 : ADCN13
Select channel ADCn.13 (PB0.15).
14 : ADCN14
Select channel ADCn.14 (PB1.0).
15 : ADCN15
Select channel ADCn.15 (PB1.1).
16 : ADCN16
Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).
17 : ADCN17
Select channel ADCn.17 (VSS).
18 : ADCN18
Select channel ADCn.18 (1.8V Output of LDO).
19 : ADCN19
Select channel ADCn.19 (VDD).
20 : ADCN20
Select channel ADCn.20 (Temperature Sensor Output).
21 : ADCN21
Select channel ADCn.21 (VIOHD / 4).
22 : ADCN22
Select channel ADCn.22 (RESERVED).
23 : ADCN23
Select channel ADCn.23 (RESERVED).
24 : ADCN24
Select channel ADCn.24 (RESERVED).
25 : ADCN25
Select channel ADCn.25 (RESERVED).
26 : ADCN26
Select channel ADCn.26 (RESERVED).
27 : ADCN27
Select channel ADCn.27 (RESERVED).
28 : ADCN28
Select channel ADCn.28 (RESERVED).
29 : ADCN29
Select channel ADCn.29 (RESERVED).
30 : ADCN30
Select channel ADCn.30 (RESERVED).
31 : END
None - End the sequence.
End of enumeration elements list.
TS2CHR : Time Slot 2 Conversion Characteristic.
bits : 16 - 17 (2 bit)
Enumeration:
0 : CC0
Select conversion characteristic 0 for time slot 2.
1 : CC1
Select conversion characteristic 1 for time slot 2.
2 : CC2
Select conversion characteristic 2 for time slot 2.
3 : CC3
Select conversion characteristic 3 for time slot 2.
End of enumeration elements list.
TS2MUX : Time Slot 2 Input Channel.
bits : 18 - 22 (5 bit)
Enumeration:
0 : ADCN0
Select channel ADCn.0 (RESERVED).
1 : ADCN1
Select channel ADCn.1 (RESERVED).
2 : ADCN2
Select channel ADCn.2 (PB0.0).
3 : ADCN3
Select channel ADCn.3 (PB0.1).
4 : ADCN4
Select channel ADCn.4 (PB0.2).
5 : ADCN5
Select channel ADCn.5 (PB0.3).
6 : ADCN6
Select channel ADCn.6 (PB0.4).
7 : ADCN7
Select channel ADCn.7 (PB0.5).
8 : ADCN8
Select channel ADCn.8 (PB0.6).
9 : ADCN9
Select channel ADCn.9 (PB0.8).
10 : ADCN10
Select channel ADCn.10 (PB0.9).
11 : ADCN11
Select channel ADCn.11 (RESERVED).
12 : ADCN12
Select channel ADCn.12 (PB0.14).
13 : ADCN13
Select channel ADCn.13 (PB0.15).
14 : ADCN14
Select channel ADCn.14 (PB1.0).
15 : ADCN15
Select channel ADCn.15 (PB1.1).
16 : ADCN16
Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).
17 : ADCN17
Select channel ADCn.17 (VSS).
18 : ADCN18
Select channel ADCn.18 (1.8V Output of LDO).
19 : ADCN19
Select channel ADCn.19 (VDD).
20 : ADCN20
Select channel ADCn.20 (Temperature Sensor Output).
21 : ADCN21
Select channel ADCn.21 (VIOHD / 4).
22 : ADCN22
Select channel ADCn.22 (RESERVED).
23 : ADCN23
Select channel ADCn.23 (RESERVED).
24 : ADCN24
Select channel ADCn.24 (RESERVED).
25 : ADCN25
Select channel ADCn.25 (RESERVED).
26 : ADCN26
Select channel ADCn.26 (RESERVED).
27 : ADCN27
Select channel ADCn.27 (RESERVED).
28 : ADCN28
Select channel ADCn.28 (RESERVED).
29 : ADCN29
Select channel ADCn.29 (RESERVED).
30 : ADCN30
Select channel ADCn.30 (RESERVED).
31 : END
None - End the sequence.
End of enumeration elements list.
TS3CHR : Time Slot 3 Conversion Characteristic.
bits : 24 - 25 (2 bit)
Enumeration:
0 : CC0
Select conversion characteristic 0 for time slot 3.
1 : CC1
Select conversion characteristic 1 for time slot 3.
2 : CC2
Select conversion characteristic 2 for time slot 3.
3 : CC3
Select conversion characteristic 3 for time slot 3.
End of enumeration elements list.
TS3MUX : Time Slot 3 Input Channel.
bits : 26 - 30 (5 bit)
Enumeration:
0 : ADCN0
Select channel ADCn.0 (RESERVED).
1 : ADCN1
Select channel ADCn.1 (RESERVED).
2 : ADCN2
Select channel ADCn.2 (PB0.0).
3 : ADCN3
Select channel ADCn.3 (PB0.1).
4 : ADCN4
Select channel ADCn.4 (PB0.2).
5 : ADCN5
Select channel ADCn.5 (PB0.3).
6 : ADCN6
Select channel ADCn.6 (PB0.4).
7 : ADCN7
Select channel ADCn.7 (PB0.5).
8 : ADCN8
Select channel ADCn.8 (PB0.6).
9 : ADCN9
Select channel ADCn.9 (PB0.8).
10 : ADCN10
Select channel ADCn.10 (PB0.9).
11 : ADCN11
Select channel ADCn.11 (RESERVED).
12 : ADCN12
Select channel ADCn.12 (PB0.14).
13 : ADCN13
Select channel ADCn.13 (PB0.15).
14 : ADCN14
Select channel ADCn.14 (PB1.0).
15 : ADCN15
Select channel ADCn.15 (PB1.1).
16 : ADCN16
Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).
17 : ADCN17
Select channel ADCn.17 (VSS).
18 : ADCN18
Select channel ADCn.18 (1.8V Output of LDO).
19 : ADCN19
Select channel ADCn.19 (VDD).
20 : ADCN20
Select channel ADCn.20 (Temperature Sensor Output).
21 : ADCN21
Select channel ADCn.21 (VIOHD / 4).
22 : ADCN22
Select channel ADCn.22 (RESERVED).
23 : ADCN23
Select channel ADCn.23 (RESERVED).
24 : ADCN24
Select channel ADCn.24 (RESERVED).
25 : ADCN25
Select channel ADCn.25 (RESERVED).
26 : ADCN26
Select channel ADCn.26 (RESERVED).
27 : ADCN27
Select channel ADCn.27 (RESERVED).
28 : ADCN28
Select channel ADCn.28 (RESERVED).
29 : ADCN29
Select channel ADCn.29 (RESERVED).
30 : ADCN30
Select channel ADCn.30 (RESERVED).
31 : END
None - End the sequence.
End of enumeration elements list.
Conversion Characteristic 2 and 3 Setup
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHR2GN : Conversion Characteristic 2 Gain.
bits : 0 - 0 (1 bit)
Enumeration:
0 : UNITY
The on-chip PGA gain is 1.
1 : HALF
The on-chip PGA gain is 0.5.
End of enumeration elements list.
CHR2RPT : Conversion Characteristic 2 Repeat Counter.
bits : 1 - 3 (3 bit)
Enumeration:
0 : ACC1
Accumulate one sample.
1 : ACC4
Accumulate four samples.
2 : ACC8
Accumulate eight samples.
3 : ACC16
Accumulate sixteen samples.
4 : ACC32
Accumulate thirty-two samples (10-bit mode only).
5 : ACC64
Accumulate sixty-four samples (10-bit mode only).
End of enumeration elements list.
CHR2LS : Conversion Characteristic 2 Left-Shift Bits.
bits : 4 - 6 (3 bit)
CHR2RSEL : Conversion Characteristic 2 Resolution Selection.
bits : 7 - 7 (1 bit)
Enumeration:
0 : B10
Select 10-bit Mode.
1 : B12
Select 12-bit Mode (burst mode must be enabled).
End of enumeration elements list.
CHR2WCIEN : Conversion Characteristic 2 Window Comparator Interrupt Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable window comparison interrupts.
1 : ENABLED
Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.
End of enumeration elements list.
CHR3GN : Conversion Characteristic 3 Gain.
bits : 16 - 16 (1 bit)
Enumeration:
0 : UNITY
The on-chip PGA gain is 1.
1 : HALF
The on-chip PGA gain is 0.5.
End of enumeration elements list.
CHR3RPT : Conversion Characteristic 3 Repeat Counter.
bits : 17 - 19 (3 bit)
Enumeration:
0 : ACC1
Accumulate one sample.
1 : ACC4
Accumulate four samples.
2 : ACC8
Accumulate eight samples.
3 : ACC16
Accumulate sixteen samples.
4 : ACC32
Accumulate thirty-two samples (10-bit mode only).
5 : ACC64
Accumulate sixty-four samples (10-bit mode only).
End of enumeration elements list.
CHR3LS : Conversion Characteristic 3 Left-Shift Bits.
bits : 20 - 22 (3 bit)
CHR3RSEL : Conversion Characteristic 3 Resolution Selection.
bits : 23 - 23 (1 bit)
Enumeration:
0 : B10
Select 10-bit Mode.
1 : B12
Select 12-bit Mode (burst mode must be enabled).
End of enumeration elements list.
CHR3WCIEN : Conversion Characteristic 3 Window Comparator Interrupt Enable.
bits : 24 - 24 (1 bit)
Enumeration:
0 : DISABLED
Disable window comparison interrupts.
1 : ENABLED
Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.
End of enumeration elements list.
Conversion Characteristic 0 and 1 Setup
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHR0GN : Conversion Characteristic 0 Gain.
bits : 0 - 0 (1 bit)
Enumeration:
0 : UNITY
The on-chip PGA gain is 1.
1 : HALF
The on-chip PGA gain is 0.5.
End of enumeration elements list.
CHR0RPT : Conversion Characteristic 0 Repeat Counter.
bits : 1 - 3 (3 bit)
Enumeration:
0 : ACC1
Accumulate one sample.
1 : ACC4
Accumulate four samples.
2 : ACC8
Accumulate eight samples.
3 : ACC16
Accumulate sixteen samples.
4 : ACC32
Accumulate thirty-two samples (10-bit mode only).
5 : ACC64
Accumulate sixty-four samples (10-bit mode only).
End of enumeration elements list.
CHR0LS : Conversion Characteristic 0 Left-Shift Bits.
bits : 4 - 6 (3 bit)
CHR0RSEL : Conversion Characteristic 0 Resolution Selection.
bits : 7 - 7 (1 bit)
Enumeration:
0 : B10
Select 10-bit Mode.
1 : B12
Select 12-bit Mode (burst mode must be enabled).
End of enumeration elements list.
CHR0WCIEN : Conversion Characteristic 0 Window Comparator Interrupt Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable window comparison interrupts.
1 : ENABLED
Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.
End of enumeration elements list.
CHR1GN : Conversion Characteristic 1 Gain.
bits : 16 - 16 (1 bit)
Enumeration:
0 : UNITY
The on-chip PGA gain is 1.
1 : HALF
The on-chip PGA gain is 0.5.
End of enumeration elements list.
CHR1RPT : Conversion Characteristic 1 Repeat Counter.
bits : 17 - 19 (3 bit)
Enumeration:
0 : ACC1
Accumulate one sample.
1 : ACC4
Accumulate four samples.
2 : ACC8
Accumulate eight samples.
3 : ACC16
Accumulate sixteen samples.
4 : ACC32
Accumulate thirty-two samples (10-bit mode only).
5 : ACC64
Accumulate sixty-four samples (10-bit mode only).
End of enumeration elements list.
CHR1LS : Conversion Characteristic 1 Left-Shift Bits.
bits : 20 - 22 (3 bit)
CHR1RSEL : Conversion Characteristic 1 Resolution Selection.
bits : 23 - 23 (1 bit)
Enumeration:
0 : B10
Select 10-bit Mode.
1 : B12
Select 12-bit Mode (burst mode must be enabled).
End of enumeration elements list.
CHR1WCIEN : Conversion Characteristic 1 Window Comparator Interrupt Enable.
bits : 24 - 24 (1 bit)
Enumeration:
0 : DISABLED
Disable window comparison interrupts.
1 : ENABLED
Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.
End of enumeration elements list.
Output Data Word
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Output Data Word.
bits : 0 - 31 (32 bit)
access : read-only
Window Comparator Limits
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCLT : Less-Than Window Comparator Limit.
bits : 0 - 15 (16 bit)
WCGT : Greater-Than Window Comparator Limit.
bits : 16 - 31 (16 bit)
Accumulator Initial Value
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACC : Accumulator Initial Value.
bits : 0 - 15 (16 bit)
access : write-only
Module Status
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCI : Window Compare Interrupt.
bits : 0 - 0 (1 bit)
Enumeration:
0 : NOT_SET
Read: A window compare interrupt has not occurred. Write: Clear the interrupt.
1 : SET
Read: A window compare interrupt occurred. Write: Force a window compare interrupt.
End of enumeration elements list.
SCCI : Single Conversion Complete Interrupt.
bits : 1 - 1 (1 bit)
Enumeration:
0 : NOT_SET
Read: A single data conversion interrupt has not occurred. Write: Clear the interrupt.
1 : SET
Read: A single data conversion interrupt occurred. Write: Force a single data conversion interrupt.
End of enumeration elements list.
SDI : Scan Done Interrupt.
bits : 2 - 2 (1 bit)
Enumeration:
0 : NOT_SET
Read: A scan done interrupt has not occurred. Write: Clear the interrupt.
1 : SET
Read: A scan done interrupt occurred. Write: Force a scan done interrupt.
End of enumeration elements list.
FORI : FIFO Overrun Interrupt.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NOT_SET
Read: A data FIFO overrun interrupt has not occurred. Write: Clear the interrupt.
1 : SET
Read: A data FIFO overrun interrupt occurred. Write: Force a data FIFO overrun interrupt.
End of enumeration elements list.
FURI : FIFO Underrun Interrupt.
bits : 4 - 4 (1 bit)
Enumeration:
0 : NOT_SET
Read: A data FIFO underrun interrupt has not occurred. Write: Clear the interrupt.
1 : SET
Read: A data FIFO underrun interrupt occurred. Write: Force a data FIFO underrun interrupt.
End of enumeration elements list.
FIFO Status
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOLVL : FIFO Level.
bits : 0 - 3 (4 bit)
access : read-only
DPSTS : Data Packing Status.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : LOWER
The next ADC conversion will be written to the lower half-word.
1 : UPPER
The next ADC conversion will be written to the upper half-word.
End of enumeration elements list.
DRDYF : Data Ready Flag.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
New data is not produced yet.
1 : SET
New data is ready.
End of enumeration elements list.
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