Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUPDT : Output Update Trigger.
bits : 0 - 2 (3 bit)
Enumeration:
0 : DACNT8
The IDAC output updates using the DACnT8 (Timer 0 Low Overflow) trigger source.
1 : DACNT9
The IDAC output updates using the DACnT9 (Timer 1 High Overflow) trigger source.
2 : DACNT10
The IDAC output updates using the DACnT10 (Timer 1 Low Overflow) trigger source.
3 : DACNT11
The IDAC output updates using the DACnT11 (Timer 1 High Overflow) trigger source.
4 : DACNT12
The IDAC output updates on the rising edge of the trigger source selected by ETRIG.
5 : DACNT13
The IDAC output updates on the falling edge of the trigger source selected by ETRIG.
6 : DACNT14
The IDAC output updates on any edge of the trigger source selected by ETRIG.
7 : DACNT15
The IDAC output updates on write to DATA register (On Demand).
End of enumeration elements list.
ETRIG : Edge Trigger Source Select.
bits : 3 - 5 (3 bit)
Enumeration:
0 : DACNT0
Select DACnT0 (PB3.2) as the IDAC external trigger source.
1 : DACNT1
Select DACnT1 (PB3.3) as the IDAC external trigger source.
2 : DACNT2
Select DACnT2 (PB3.5) as the IDAC external trigger source.
3 : DACNT3
Select DACnT3 (PB3.6) as the IDAC external trigger source.
4 : DACNT4
Select DACnT4 (PB3.7) as the IDAC external trigger source.
5 : DACNT5
Select DACnT5 (PB3.8) as the IDAC external trigger source.
6 : DACNT6
Select DACnT6 (PB3.9) as the IDAC external trigger source.
7 : DACNT7
Select DACnT7 (SSG0 EX3) as the IDAC external trigger source.
End of enumeration elements list.
OUTMD : Output Mode.
bits : 6 - 7 (2 bit)
Enumeration:
0 : 0P5_MA
The full-scale output current is 0.5 mA.
1 : 1_MA
The full-scale output current is 1 mA.
2 : 2_MA
The full-scale output current is 2 mA.
End of enumeration elements list.
INFMT : Data Input Format.
bits : 8 - 9 (2 bit)
Enumeration:
0 : 1_10_BIT
Writes are interpreted as one 10-bit sample.
1 : 2_10_BIT
Writes are interpreted as two 10-bit samples.
2 : 4_8_BIT
Writes are interpreted as four 8-bit samples.
End of enumeration elements list.
DMARUN : DMA Run.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Read: No DMA operations are occurring or the DMA is done. Write: No effect.
1 : ENABLED
Read: A DMA operation is currently in progress. Write: Start a DMA operation.
End of enumeration elements list.
JSEL : Data Justification Select.
bits : 11 - 11 (1 bit)
Enumeration:
0 : RIGHT
Data is right-justified.
1 : LEFT
Data is left-justified.
End of enumeration elements list.
BUFRESET : Data Buffer Reset.
bits : 12 - 12 (1 bit)
access : write-only
Enumeration:
1 : RESET
Initiate a data buffer reset.
End of enumeration elements list.
TRIGINH : Trigger Source Inhibit.
bits : 13 - 13 (1 bit)
Enumeration:
0 : INACTIVE
The selected trigger source will cause the IDAC output to update.
1 : ACTIVE
The selected trigger source will not update the IDAC output, except for On-Demand DATA writes.
End of enumeration elements list.
WRAPEN : Wrap Mode Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
The IDAC will not wrap when it reaches the end of the data buffer.
1 : ENABLED
The IDAC will cycle through the data buffer contents.
End of enumeration elements list.
ORIEN : FIFO Overrun Interrupt Enable.
bits : 20 - 20 (1 bit)
Enumeration:
0 : DISABLED
Disable the FIFO overrun interrupt (ORI).
1 : ENABLED
Enable the FIFO overrun interrupt (ORI).
End of enumeration elements list.
URIEN : FIFO Underrun Interrupt Enable.
bits : 21 - 21 (1 bit)
Enumeration:
0 : DISABLED
Disable the FIFO underrun interrupt (URI).
1 : ENABLED
Enable the FIFO underrun interrupt (URI).
End of enumeration elements list.
WEIEN : FIFO Went Empty Interrupt Enable.
bits : 22 - 22 (1 bit)
Enumeration:
0 : DISABLED
Disable the FIFO went empty interrupt (WEI).
1 : ENABLED
Enable the FIFO went empty interrupt (WEI).
End of enumeration elements list.
DBGMD : IDAC Debug Mode.
bits : 29 - 29 (1 bit)
Enumeration:
0 : RUN
The IDAC module will continue to operate while the core is halted in debug mode.
1 : HALT
A debug breakpoint will cause the IDAC module to halt.
End of enumeration elements list.
LOADEN : Load Resistor Enable.
bits : 30 - 30 (1 bit)
Enumeration:
0 : DISABLED
Disable the internal load resistor.
1 : ENABLED
Enable the internal load resistor.
End of enumeration elements list.
IDACEN : IDAC Enable.
bits : 31 - 31 (1 bit)
Enumeration:
0 : DISABLED
Disable the IDAC.
1 : ENABLED
Enable the IDAC.
End of enumeration elements list.
Output Data
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Output Data.
bits : 0 - 31 (32 bit)
FIFO Buffer Status
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEVEL : FIFO Level.
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : EMPTY
The data FIFO is empty.
1 : 1WORD
The data FIFO contains one word.
2 : 2WORDS
The data FIFO contains two words.
3 : 3WORDS
The data FIFO contains three words.
4 : 4WORDS
The data FIFO is full and contains four words.
End of enumeration elements list.
ORI : FIFO Overrun Interrupt Flag.
bits : 4 - 4 (1 bit)
Enumeration:
0 : NOT_SET
Read: A FIFO overrun has not occurred. Write: Clear the interrupt.
1 : SET
Read: A FIFO overrun occurred. Write: Force a FIFO overrun interrupt.
End of enumeration elements list.
URI : FIFO Underrun Interrupt Flag.
bits : 5 - 5 (1 bit)
Enumeration:
0 : NOT_SET
Read: A FIFO underrun has not occurred. Write: Clear the interrupt.
1 : SET
Read: A FIFO underrun occurred. Write: Force a FIFO underrun interrupt.
End of enumeration elements list.
WEI : FIFO Went Empty Interrupt Flag.
bits : 6 - 6 (1 bit)
Enumeration:
0 : NOT_SET
Read: A FIFO went empty condition has not occurred. Write: Clear the interrupt.
1 : SET
Read: The FIFO is empty. Write: Force a FIFO went empty interrupt.
End of enumeration elements list.
FIFO Buffer Entries 0 and 1
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFFER0 : FIFO Buffer Entry 0.
bits : 0 - 15 (16 bit)
access : read-only
BUFFER1 : FIFO Buffer Entry 1.
bits : 16 - 31 (16 bit)
access : read-only
FIFO Buffer Entries 2 and 3
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFFER2 : FIFO Buffer Entry 2.
bits : 0 - 15 (16 bit)
access : read-only
BUFFER3 : FIFO Buffer Entry 3.
bits : 16 - 31 (16 bit)
access : read-only
Output Current Gain Adjust
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAINADJ : Output Current Gain Adjust.
bits : 0 - 4 (5 bit)
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