Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Count Mode.
bits : 0 - 1 (2 bit)
Enumeration:
0 : FREE
The timer is free running mode on the RTCn module clock (RTCnOSC or LFOSCn).
1 : RISING_EDGE
The timer is incremented on the rising edges of the selected external trigger (LPTnTx).
2 : FALLING_EDGE
The timer is incremented on the falling edges of the selected external trigger (LPTnTx).
3 : ANY_EDGE
The timer is incremented on both edges of the selected external trigger (LPTnTx).
End of enumeration elements list.
EXTSEL : External Trigger Source Select.
bits : 4 - 7 (4 bit)
Enumeration:
0 : LPTNT0
Select external trigger LPTnT0 (PB3.2).
1 : LPTNT1
Select external trigger LPTnT1 (PB3.8).
2 : LPTNT2
Select external trigger LPTnT2 (PB3.9).
3 : LPTNT3
Select external trigger LPTnT3 (Comparator 0 Output).
4 : LPTNT4
Select external trigger LPTnT4 (RESERVED).
5 : LPTNT5
Select external trigger LPTnT5 (RESERVED).
6 : LPTNT6
Select external trigger LPTnT6 (RESERVED).
7 : LPTNT7
Select external trigger LPTnT7 (RESERVED).
8 : LPTNT8
Select external trigger LPTnT8 (RESERVED).
9 : LPTNT9
Select external trigger LPTnT9 (RESERVED).
10 : LPTNT10
Select external trigger LPTnT10 (RESERVED).
11 : LPTNT11
Select external trigger LPTnT11 (RESERVED).
12 : LPTNT12
Select external trigger LPTnT12 (RESERVED).
13 : LPTNT13
Select external trigger LPTnT13 (RESERVED).
14 : LPTNT14
Select external trigger LPTnT14 (RESERVED).
15 : LPTNT15
Select external trigger LPTnT15 (RESERVED).
End of enumeration elements list.
TMRSET : Timer Set.
bits : 8 - 8 (1 bit)
Enumeration:
1 : SET
Writing a 1 to TMRSET initiates a copy of the value from the DATA register into the internal timer register. This field is automatically cleared by hardware when the copy is complete and does not need to be cleared by software.
End of enumeration elements list.
TMRCAP : Timer Capture.
bits : 9 - 9 (1 bit)
Enumeration:
1 : SET
Writing a 1 to TMRCAP initiates a read of internal timer register into the DATA register. This field is automatically cleared by hardware when the operation completes and does not need to be cleared by software.
End of enumeration elements list.
CMPSET : Timer Comparator Set.
bits : 10 - 10 (1 bit)
Enumeration:
1 : SET
Writing a 1 to CMPSET initiates a copy of the value in DATA into the internal timer comparator register. This field is automatically cleared by hardware when the copy is complete and does not need to be cleared by software.
End of enumeration elements list.
CMPCAP : Timer Comparator Capture.
bits : 11 - 11 (1 bit)
Enumeration:
1 : SET
Writing a 1 to CMPCAP initiates a read of the internal comparator register into the DATA register. This field is automatically cleared by hardware when the operation completes and does not need to be cleared by software.
End of enumeration elements list.
OVFIEN : Timer Overflow Interrupt Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
Disable the timer overflow interrupt.
1 : ENABLED
Enable the timer overflow interrupt.
End of enumeration elements list.
CMPIEN : Timer Compare Event Interrupt Enable.
bits : 17 - 17 (1 bit)
Enumeration:
0 : DISABLED
Disable the timer compare event interrupt.
1 : ENABLED
Enable the timer compare event interrupt.
End of enumeration elements list.
OVFTMD : Timer Overflow Toggle Mode.
bits : 18 - 18 (1 bit)
Enumeration:
0 : DISABLED
Timer overflows do not toggle the Low Power Timer output.
1 : ENABLED
Timer overflows toggle the Low Power Timer output.
End of enumeration elements list.
CMPTMD : Timer Compare Event Toggle Mode .
bits : 19 - 19 (1 bit)
Enumeration:
0 : DISABLED
Timer compare events do not toggle the Low Power Timer output.
1 : ENABLED
Timer compare events toggle the Low Power Timer output.
End of enumeration elements list.
CMPRSTEN : Timer Compare Event Reset Enable.
bits : 24 - 24 (1 bit)
Enumeration:
0 : DISABLED
Timer compare events do not reset the timer.
1 : ENABLED
Timer compare events reset the timer.
End of enumeration elements list.
DBGMD : Low Power Timer Debug Mode.
bits : 30 - 30 (1 bit)
Enumeration:
0 : RUN
The Low Power Timer module will continue to operate while the core is halted in debug mode.
1 : HALT
A debug breakpoint will cause the Low Power Timer module to halt.
End of enumeration elements list.
RUN : Timer Run Control and Compare Threshold Enable.
bits : 31 - 31 (1 bit)
Enumeration:
0 : STOP
Stop the timer and disable the compare threshold.
1 : START
Start the timer running and enable the compare threshold.
End of enumeration elements list.
Timer and Comparator Data
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Timer and Comparator Data.
bits : 0 - 15 (16 bit)
Module Status
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVFI : Timer Overflow Interrupt Flag.
bits : 0 - 0 (1 bit)
Enumeration:
0 : NOT_SET
A timer overflow has not occurred.
1 : SET
A timer overflow occurred.
End of enumeration elements list.
CMPI : Timer Compare Event Interrupt Flag.
bits : 1 - 1 (1 bit)
Enumeration:
0 : NOT_SET
A timer compare event has not occurred.
1 : SET
A timer compare event occurred.
End of enumeration elements list.
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