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PBCFG_0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONTROL0

CONTROL1

XBAR0L

XBAR0H

XBAR1

PBKEY


CONTROL0

Global Port Control 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL0 CONTROL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT0SEL INT0POL INT0MD INT0EN INT1SEL INT1POL INT1MD INT1EN PGTIMER PGDONEF

INT0SEL : External Interrupt 0 Pin Selection.
bits : 0 - 3 (4 bit)

Enumeration:

0 : INT0_0

Select INT0.0 (PB2.0)

1 : INT0_1

Select INT0.1 (PB2.1)

2 : INT0_2

Select INT0.2 (PB2.2)

3 : INT0_3

Select INT0.3 (PB2.3)

4 : INT0_4

Select INT0.4 (PB3.3)

5 : INT0_5

Select INT0.5 (PB3.4)

6 : INT0_6

Select INT0.6 (PB3.5)

7 : INT0_7

Select INT0.7 (PB3.6)

8 : INT0_8

Select INT0.8 (PB3.7)

9 : INT0_9

Select INT0.9 (PB3.8)

10 : INT0_10

Select INT0.10 (PB3.9)

11 : INT0_11

Select INT0.11 (RESERVED)

12 : INT0_12

Select INT0.12 (RESERVED)

13 : INT0_13

Select INT0.13 (RESERVED)

14 : INT0_14

Select INT0.14 (RESERVED)

15 : INT0_15

Select INT0.15 (RESERVED)

End of enumeration elements list.

INT0POL : External Interrupt 0 Polarity.
bits : 4 - 4 (1 bit)

Enumeration:

0 : LOW

A low value or falling edge on the selected pin will cause interrupt.

1 : HIGH

A high value or rising edge on the selected pin will cause interrupt.

End of enumeration elements list.

INT0MD : External Interrupt 0 Mode.
bits : 5 - 5 (1 bit)

Enumeration:

0 : LEVEL

Interrupt based on level sensitivity.

1 : EDGE

Interrupt based on edge sensitivity.

End of enumeration elements list.

INT0EN : External Interrupt 0 Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : DISABLED

Disable external interrupt 0.

1 : ENABLED

Enable external interrupt 0.

End of enumeration elements list.

INT1SEL : External Interrupt 1 Pin Selection.
bits : 8 - 11 (4 bit)

Enumeration:

0 : INT1_0

Select INT1.0 (PB2.0)

1 : INT1_1

Select INT1.1 (PB2.1)

2 : INT1_2

Select INT1.2 (PB2.2)

3 : INT1_3

Select INT1.3 (PB2.3)

4 : INT1_4

Select INT1.4 (PB3.3)

5 : INT1_5

Select INT1.5 (PB3.4)

6 : INT1_6

Select INT1.6 (PB3.5)

7 : INT1_7

Select INT1.7 (PB3.6)

8 : INT1_8

Select INT1.8 (PB3.7)

9 : INT1_9

Select INT1.9 (PB3.8)

10 : INT1_10

Select INT1.10 (PB3.9)

11 : INT1_11

Select INT1.11 (RESERVED)

12 : INT1_12

Select INT1.12 (RESERVED)

13 : INT1_13

Select INT1.13 (RESERVED)

14 : INT1_14

Select INT1.14 (RESERVED)

15 : INT1_15

Select INT1.15 (RESERVED)

End of enumeration elements list.

INT1POL : External Interrupt 1 Polarity.
bits : 12 - 12 (1 bit)

Enumeration:

0 : LOW

A low value or falling edge on the selected pin will cause interrupt.

1 : HIGH

A high value or rising edge on the selected pin will cause interrupt.

End of enumeration elements list.

INT1MD : External Interrupt 1 Mode.
bits : 13 - 13 (1 bit)

Enumeration:

0 : LEVEL

Interrupt based on level sensitivity.

1 : EDGE

Interrupt based on edge sensitivity.

End of enumeration elements list.

INT1EN : External Interrupt 1 Enable.
bits : 15 - 15 (1 bit)

Enumeration:

0 : DISABLED

Disable external interrupt 1.

1 : ENABLED

Enable external interrupt 1.

End of enumeration elements list.

PGTIMER : Pulse Generator Timer.
bits : 24 - 28 (5 bit)

PGDONEF : Pulse Generator Timer Done Flag.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

Firmware has written to the PBPGPHASE register, but the Pulse Generator timer has not expired.

1 : SET

The Pulse Generator cycle finished since the last time PBPGPHASE was written.

End of enumeration elements list.


CONTROL1

Global Port Control 1
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL1 CONTROL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JTAGEN ETMEN EMIFBE0BEN EMIFCS1EN EMIFEN EMIFWIDTH MATMD EVREGRMD LOCK

JTAGEN : JTAG Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : DISABLED

JTAG functionality is not pinned out.

1 : ENABLED

JTAG functionality is pinned out.

End of enumeration elements list.

ETMEN : ETM Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : DISABLED

ETM not pinned out.

1 : ENABLED

ETM is enabled and pinned out.

End of enumeration elements list.

EMIFBE0BEN : EMIF BE0 Pin Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : DISABLED

Disable the EMIF /BE0 pin.

1 : ENABLED

Enable the /BE0 pin if EMIFEN is also set to 1.

End of enumeration elements list.

EMIFCS1EN : EMIF CS1 Pin Enable.
bits : 8 - 8 (1 bit)

Enumeration:

0 : DISABLED

Disable the EMIF CS1 pin.

1 : ENABLED

Enable the CS1 pin if EMIFEN is also set to 1.

End of enumeration elements list.

EMIFEN : EMIF Enable.
bits : 9 - 9 (1 bit)

Enumeration:

0 : DISABLED

Disable the EMIF pins.

1 : ENABLED

EMIF is enabled and pinned out.

End of enumeration elements list.

EMIFWIDTH : EMIF Width.
bits : 10 - 15 (6 bit)

Enumeration:

0 : AWIDTH_8

EMIF Address[7:0]

1 : AWIDTH_9

EMIF Address[8:0], PB2.8 = A[8]

2 : AWIDTH_10

EMIF Address[9:0], PB2.7 = A[9]

3 : AWIDTH_11

EMIF Address[10:0], PB2.6 = A[10]

4 : AWIDTH_12

EMIF Address[11:0], PB2.5 = A[11]

5 : AWIDTH_13

EMIF Address[12:0], PB2.4 = A[12]

6 : AWIDTH_14

EMIF Address[13:0], PB2.3 = A[13]

7 : AWIDTH_15

EMIF Address[14:0], PB2.2 = A[14]

8 : AWIDTH_16

EMIF Address[15:0], PB2.1 = A[15]

9 : AWIDTH_17

EMIF Address[16:0], PB2.0 = A[16]

10 : AWIDTH_18

EMIF Address[17:0], PB1.15 = A[17]

11 : AWIDTH_19

EMIF Address[18:0], PB1.14 = A[18]

12 : AWIDTH_20

EMIF Address[19:0], PB1.13 = A[19]

13 : AWIDTH_21

EMIF Address[20:0], PB1.12 = A[20]

14 : AWIDTH_22

EMIF Address[21:0], PB1.11 = A[21]

15 : AWIDTH_23

EMIF Address[22:0], PB1.10 = A[22]

16 : AWIDTH_24

EMIF Address[23:0], PB1.10 = A[23]

End of enumeration elements list.

MATMD : Match Mode.
bits : 16 - 17 (2 bit)

Enumeration:

0 : PINMATCH

Port Match registers used to provide interrupt / wake sources.

1 : CAPSENSE_TX

Port Match registers used to monitor output pin activity for Capacitive Sensing measurements.

2 : CAPSENSE_RX

Port Match registers used to monitor input pin activity for Capacitive Sensing measurements.

3 : RESERVED

Reserved.

End of enumeration elements list.

EVREGRMD : External Regulator Reset Mode.
bits : 23 - 23 (1 bit)

Enumeration:

0 : RESET_ON_ANY

The pins used by the external regulator will default to digital inputs with weak pull-up enabled on any reset.

1 : RESET_ON_POR

The pins used by the external regulator will default to digital inputs with weak pull-up enabled only on Power-On Reset. Their configured mode will be preserved through all other resets.

End of enumeration elements list.

LOCK : Port Bank Configuration Lock.
bits : 31 - 31 (1 bit)

Enumeration:

0 : UNLOCKED

Port Bank Configuration and Control registers are unlocked.

1 : LOCKED

The following registers are locked from write access: CONTROL1, XBAR0L, XBAR0H, XBAR1, and all PBSKIP registers.

End of enumeration elements list.


XBAR0L

Crossbar 0 Control (Low)
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XBAR0L XBAR0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART0EN USART0FCEN USART0CEN SPI0EN SPI0NSSEN USART1EN USART1FCEN USART1CEN EPCA0EN PCA0EN PCA1EN EECI0EN ECI0EN ECI1EN I2S0TXEN I2C0EN CMP0SEN CMP0AEN CMP1SEN CMP1AEN TMR0CTEN TMR0EXEN TMR1CTEN TMR1EXEN

USART0EN : USART0 Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : DISABLED

Disable USART0 RX and TX on Crossbar 0.

1 : ENABLED

Enable USART0 RX and TX on Crossbar 0.

End of enumeration elements list.

USART0FCEN : USART0 Flow Control Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : DISABLED

Disable USART0 flow control on Crossbar 0.

1 : ENABLED

Enable USART0 flow control on Crossbar 0.

End of enumeration elements list.

USART0CEN : USART0 Clock Signal Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : DISABLED

Disable USART0 clock on Crossbar 0.

1 : ENABLED

Enable USART0 clock on Crossbar 0.

End of enumeration elements list.

SPI0EN : SPI0 Enable.
bits : 3 - 3 (1 bit)

Enumeration:

0 : DISABLED

Disable SPI0 SCK, MISO, and MOSI on Crossbar 0.

1 : ENABLED

Enable SPI0 SCK, MISO, and MOSI on Crossbar 0.

End of enumeration elements list.

SPI0NSSEN : SPI0 NSS Pin Enable.
bits : 4 - 4 (1 bit)

Enumeration:

0 : DISABLED

Disable SPI0 NSS on Crossbar 0.

1 : ENABLED

Enable SPI0 NSS on Crossbar 0.

End of enumeration elements list.

USART1EN : USART1 Enable.
bits : 5 - 5 (1 bit)

Enumeration:

0 : DISABLED

Disable USART1 RX and TX on Crossbar 0.

1 : ENABLED

Enable USART1 RX and TX on Crossbar 0.

End of enumeration elements list.

USART1FCEN : USART1 Flow Control Enable.
bits : 6 - 6 (1 bit)

Enumeration:

0 : DISABLED

Disable USART1 flow control on Crossbar 0.

1 : ENABLED

Enable USART1 flow control on Crossbar 0.

End of enumeration elements list.

USART1CEN : USART1 Clock Signal Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : DISABLED

Disable USART1 clock on Crossbar 0.

1 : ENABLED

Enable USART1 clock on Crossbar 0.

End of enumeration elements list.

EPCA0EN : EPCA0 Channel Enable.
bits : 8 - 10 (3 bit)

Enumeration:

0 : NONE

Disable all EPCA0 channels on Crossbar 0.

1 : STD_CEX0

Enable EPCA0 STD_CEX0 on Crossbar 0.

2 : STD_CEX0_1

Enable EPCA0 STD_CEX0 and STD_CEX1 on Crossbar 0.

3 : STD_CEX0_2

Enable EPCA0 STD_CEX0, STD_CEX1, and STD_CEX2 on Crossbar 0.

4 : STD_CEX0_3

Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, and STD_CEX3 on Crossbar 0.

5 : STD_CEX0_4

Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3, and STD_CEX4 on Crossbar 0.

6 : STD_CEX0_5

Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3, STD_CEX4, and STD_CEX5 on Crossbar 0.

End of enumeration elements list.

PCA0EN : PCA0 Channel Enable.
bits : 14 - 15 (2 bit)

Enumeration:

0 : NONE

Disable all PCA0 channels on Crossbar 0.

1 : CEX0

Enable PCA0 CEX0 on Crossbar 0.

3 : CEX0_1

Enable PCA0 CEX0 and CEX1 on Crossbar 0.

End of enumeration elements list.

PCA1EN : PCA1 Channel Enable.
bits : 16 - 17 (2 bit)

Enumeration:

0 : NONE

Disable all PCA1 channels on Crossbar 0.

1 : CEX0

Enable PCA1 CEX0 on Crossbar 0.

3 : CEX0_1

Enable PCA1 CEX0 and CEX1 on Crossbar 0.

End of enumeration elements list.

EECI0EN : EPCA0 ECI Enable.
bits : 18 - 18 (1 bit)

Enumeration:

0 : DISABLED

Disable EPCA0 ECI on Crossbar 0.

1 : ENABLED

Enable EPCA0 ECI on Crossbar 0.

End of enumeration elements list.

ECI0EN : PCA0 ECI Enable.
bits : 19 - 19 (1 bit)

Enumeration:

0 : DISABLED

Disable PCA0 ECI on Crossbar 0.

1 : ENABLED

Enable PCA0 ECI on Crossbar 0.

End of enumeration elements list.

ECI1EN : PCA1 ECI Enable.
bits : 20 - 20 (1 bit)

Enumeration:

0 : DISABLED

Disable PCA1 ECI on Crossbar 0.

1 : ENABLED

Enable PCA1 ECI on Crossbar 0.

End of enumeration elements list.

I2S0TXEN : I2S0 TX Enable.
bits : 21 - 21 (1 bit)

Enumeration:

0 : DISABLED

Disable I2S0 TX on Crossbar 0.

1 : ENABLED

Enable I2S0 TX on Crossbar 0.

End of enumeration elements list.

I2C0EN : I2C0 Enable.
bits : 22 - 22 (1 bit)

Enumeration:

0 : DISABLED

Disable I2C0 SDA and SCL on Crossbar 0.

1 : ENABLED

Enable I2C0 SDA and SCL on Crossbar 0.

End of enumeration elements list.

CMP0SEN : Comparator 0 Synchronous Output (CMP0S) Enable.
bits : 23 - 23 (1 bit)

Enumeration:

0 : DISABLED

Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.

1 : ENABLED

Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.

End of enumeration elements list.

CMP0AEN : Comparator 0 Asynchronous Output (CMP0A) Enable.
bits : 24 - 24 (1 bit)

Enumeration:

0 : DISABLED

Disable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.

1 : ENABLED

Enable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.

End of enumeration elements list.

CMP1SEN : Comparator 1 Synchronous Output (CMP1S) Enable.
bits : 25 - 25 (1 bit)

Enumeration:

0 : DISABLED

Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.

1 : ENABLED

Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.

End of enumeration elements list.

CMP1AEN : Comparator 1 Asynchronous Output (CMP1A) Enable.
bits : 26 - 26 (1 bit)

Enumeration:

0 : DISABLED

Disable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.

1 : ENABLED

Enable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.

End of enumeration elements list.

TMR0CTEN : TIMER0 T0CT Enable.
bits : 27 - 27 (1 bit)

Enumeration:

0 : DISABLED

Disable TIMER0 CT on Crossbar 0.

1 : ENABLED

Enable TIMER0 CT on Crossbar 0.

End of enumeration elements list.

TMR0EXEN : TIMER0 T0EX Enable.
bits : 28 - 28 (1 bit)

Enumeration:

0 : DISABLED

Disable TIMER0 EX on Crossbar 0.

1 : ENABLED

Enable TIMER0 EX on Crossbar 0.

End of enumeration elements list.

TMR1CTEN : TIMER1 T1CT Enable.
bits : 29 - 29 (1 bit)

Enumeration:

0 : DISABLED

Disable TIMER1 CT on Crossbar 0.

1 : ENABLED

Enable TIMER1 CT on Crossbar 0.

End of enumeration elements list.

TMR1EXEN : TIMER1 T1EX Enable.
bits : 30 - 30 (1 bit)

Enumeration:

0 : DISABLED

Disable TIMER1 EX on Crossbar 0.

1 : ENABLED

Enable TIMER1 EX on Crossbar 0.

End of enumeration elements list.


XBAR0H

Crossbar 0 Control (High)
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XBAR0H XBAR0H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART0EN UART0FCEN UART1EN SPI1EN SPI1NSSEN SPI2EN SPI2NSSEN AHBEN XBAR0EN

UART0EN : UART0 Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : DISABLED

Disable UART0 RX and TX on Crossbar 0.

1 : ENABLED

Enable UART0 RX and TX on Crossbar 0.

End of enumeration elements list.

UART0FCEN : UART0 Flow Control Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : DISABLED

Disable UART0 flow control on Crossbar 0.

1 : ENABLED

Enable UART0 flow control on Crossbar 0.

End of enumeration elements list.

UART1EN : UART1 Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : DISABLED

Disable UART1 RX and TX on Crossbar 0.

1 : ENABLED

Enable UART1 RX and TX on Crossbar 0.

End of enumeration elements list.

SPI1EN : SPI1 Enable.
bits : 3 - 3 (1 bit)

Enumeration:

0 : DISABLED

Disable SPI1 SCK, MISO, and MOSI on Crossbar 0.

1 : ENABLED

Enable SPI1 SCK, MISO, and MOSI on Crossbar 0.

End of enumeration elements list.

SPI1NSSEN : SPI1 NSS Pin Enable.
bits : 4 - 4 (1 bit)

Enumeration:

0 : DISABLED

Disable SPI1 NSS on Crossbar 0.

1 : ENABLED

Enable SPI1 NSS on Crossbar 0.

End of enumeration elements list.

SPI2EN : SPI2 Enable.
bits : 5 - 5 (1 bit)

Enumeration:

0 : DISABLED

Disable SPI2 SCK, MISO, and MOSI on Crossbar 0.

1 : ENABLED

Enable SPI2 SCK, MISO, and MOSI on Crossbar 0.

End of enumeration elements list.

SPI2NSSEN : SPI2 NSS Pin Enable.
bits : 6 - 6 (1 bit)

Enumeration:

0 : DISABLED

Disable SPI2 NSS on Crossbar 0.

1 : ENABLED

Enable SPI2 NSS on Crossbar 0.

End of enumeration elements list.

AHBEN : AHB Clock Output Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : DISABLED

Disable the AHB Clock / 16 output on Crossbar 0.

1 : ENABLED

Enable the AHB Clock / 16 output on Crossbar 0.

End of enumeration elements list.

XBAR0EN : Crossbar 0 Enable.
bits : 31 - 31 (1 bit)

Enumeration:

0 : DISABLED

Disable Crossbar 0.

1 : ENABLED

Enable Crossbar 0.

End of enumeration elements list.


XBAR1

Crossbar 1 Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XBAR1 XBAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSG0EN CMP0SEN CMP1SEN SPI1EN SPI1NSSEN RTC0EN SPI2EN SPI2NSSEN USART1EN USART1FCEN USART1CEN UART0EN UART0FCEN I2S0TXEN I2C0EN UART1EN I2S0RXEN LPT0OEN I2C1EN KILLHDEN XBAR1EN

SSG0EN : SSG0 Enable.
bits : 0 - 1 (2 bit)

Enumeration:

0 : NONE

Disable all SSG0 channels on Crossbar 1.

1 : EX0

Enable SSG0 EX0 on Crossbar 1.

2 : EX0_1

Enable SSG0 EX0 and EX1 on Crossbar 1.

3 : EX0_3

Enable SSG0 EX0, EX1, EX2, and EX3 on Crossbar 1.

End of enumeration elements list.

CMP0SEN : Comparator 0 Synchronous Output (CMP0S) Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : DISABLED

Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1.

1 : ENABLED

Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1.

End of enumeration elements list.

CMP1SEN : Comparator 1 Synchronous Output (CMP1S) Enable.
bits : 3 - 3 (1 bit)

Enumeration:

0 : DISABLED

Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1.

1 : ENABLED

Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1.

End of enumeration elements list.

SPI1EN : SPI1 Enable.
bits : 4 - 4 (1 bit)

Enumeration:

0 : DISABLED

Disable SPI1 SCK, MISO, and MOSI on Crossbar 1.

1 : ENABLED

Enable SPI1 SCK, MISO, and MOSI on Crossbar 1.

End of enumeration elements list.

SPI1NSSEN : SPI1 NSS Pin Enable.
bits : 5 - 5 (1 bit)

Enumeration:

0 : DISABLED

Disable SPI1 NSS on Crossbar 1.

1 : ENABLED

Enable SPI1 NSS on Crossbar 1.

End of enumeration elements list.

RTC0EN : RTC0 Output Enable.
bits : 6 - 6 (1 bit)

Enumeration:

0 : DISABLED

Disable RTC0 Output on Crossbar 1.

1 : ENABLED

Enable RTC0 Output on Crossbar 1.

End of enumeration elements list.

SPI2EN : SPI2 Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : DISABLED

Disable SPI2 SCK, MISO, and MOSI on Crossbar 1.

1 : ENABLED

Enable SPI2 SCK, MISO, and MOSI on Crossbar 1.

End of enumeration elements list.

SPI2NSSEN : SPI2 NSS Pin Enable.
bits : 8 - 8 (1 bit)

Enumeration:

0 : DISABLED

Disable SPI2 NSS on Crossbar 1.

1 : ENABLED

Enable SPI2 NSS on Crossbar 1.

End of enumeration elements list.

USART1EN : USART1 Enable.
bits : 9 - 9 (1 bit)

Enumeration:

0 : DISABLED

Disable USART1 RX and TX on Crossbar 1.

1 : ENABLED

Enable USART1 RX and TX on Crossbar 1.

End of enumeration elements list.

USART1FCEN : USART1 Flow Control Enable.
bits : 10 - 10 (1 bit)

Enumeration:

0 : DISABLED

Disable USART1 flow control on Crossbar 1.

1 : ENABLED

Enable USART1 flow control on Crossbar 1.

End of enumeration elements list.

USART1CEN : USART1 Clock Signal Enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : DISABLED

Disable USART1 clock on Crossbar 1.

1 : ENABLED

Enable USART1 clock on Crossbar 1.

End of enumeration elements list.

UART0EN : UART0 Enable.
bits : 12 - 12 (1 bit)

Enumeration:

0 : DISABLED

Disable UART0 RX and TX on Crossbar 1.

1 : ENABLED

Enable UART0 RX and TX on Crossbar 1.

End of enumeration elements list.

UART0FCEN : UART0 Flow Control Enable.
bits : 13 - 13 (1 bit)

Enumeration:

0 : DISABLED

Disable UART0 flow control on Crossbar 1.

1 : ENABLED

Enable UART0 flow control on Crossbar1.

End of enumeration elements list.

I2S0TXEN : I2S0 TX Enable.
bits : 14 - 14 (1 bit)

Enumeration:

0 : DISABLED

Disable I2S0 TX on Crossbar 1.

1 : ENABLED

Enable I2S0 TX on Crossbar 1.

End of enumeration elements list.

I2C0EN : I2C0 Enable.
bits : 15 - 15 (1 bit)

Enumeration:

0 : DISABLED

Disable I2C0 SDA and SCL on Crossbar 1.

1 : ENABLED

Enable I2C0 SDA and SCL on Crossbar 1.

End of enumeration elements list.

UART1EN : UART1 Enable.
bits : 16 - 16 (1 bit)

Enumeration:

0 : DISABLED

Disable UART1 RX and TX on Crossbar 1.

1 : ENABLED

Enable UART1 RX and TX on Crossbar 1.

End of enumeration elements list.

I2S0RXEN : I2S0 RX Enable.
bits : 17 - 17 (1 bit)

Enumeration:

0 : DISABLED

Disable I2S0 RX on Crossbar 1.

1 : ENABLED

Enable I2S0 RX on Crossbar 1.

End of enumeration elements list.

LPT0OEN : LPTIMER0 Output Enable.
bits : 19 - 19 (1 bit)

Enumeration:

0 : DISABLED

Disable LPTIMER0 Output on Crossbar 1.

1 : ENABLED

Enable LPTIMER0 Output on Crossbar 1.

End of enumeration elements list.

I2C1EN : I2C1 Enable.
bits : 20 - 20 (1 bit)

Enumeration:

0 : DISABLED

Disable I2C1 SDA and SCL on Crossbar 1.

1 : ENABLED

Enable I2C1 SDA and SCL on Crossbar 1.

End of enumeration elements list.

KILLHDEN : High Drive Kill Pin Enable.
bits : 21 - 21 (1 bit)

Enumeration:

0 : DISABLED

Disable the PB High Drive Kill Pin on Crossbar 1.

1 : ENABLED

Enable the PB High Drive Kill Pin on Crossbar 1.

End of enumeration elements list.

XBAR1EN : Crossbar 1 Enable.
bits : 31 - 31 (1 bit)

Enumeration:

0 : DISABLED

Disable Crossbar 1.

1 : ENABLED

Enable Crossbar 1.

End of enumeration elements list.


PBKEY

Global Port Key
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBKEY PBKEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : Port Bank 2, 3, and 4 Key.
bits : 0 - 7 (8 bit)

Enumeration:

0 : LOCKED

Port Bank 2, 3, and 4 registers are locked and no valid values have been written to PBKEY.

1 : INTERMEDIATE

Port Bank 2, 3, and 4 registers are locked and the first valid value (0xA5) has been written to PBKEY.

2 : UNLOCKED

Port Bank 2, 3, and 4 registers are unlocked. Any subsequent writes to the Port Bank 2, 3, or 4 registers or PBKEY will lock the interface.

End of enumeration elements list.



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