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USART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONFIG

MODE

FLOWCN

CONTROL

IPDELAY

BAUDRATE

FIFOCN

DATA


CONFIG

Module Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTRTEN RPAREN RSTPEN RSTPMD RPARMD RDATLN RSCEN RIRDAEN RINVEN RSYNCEN TSTRTEN TPAREN TSTPEN TSTPMD TPARMD TDATLN TSCEN TIRDAEN TINVEN TSYNCEN

RSTRTEN : Receiver Start Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : DISABLED

Do not expect a start bit during receptions.

1 : ENABLED

Expect a start bit during receptions.

End of enumeration elements list.

RPAREN : Receiver Parity Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : DISABLED

Do not expect a parity bit during receptions.

1 : ENABLED

Expect a parity bit during receptions.

End of enumeration elements list.

RSTPEN : Receiver Stop Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : DISABLED

Do not expect stop bits during receptions.

1 : ENABLED

Expect stop bits during receptions.

End of enumeration elements list.

RSTPMD : Receiver Stop Mode.
bits : 3 - 4 (2 bit)

Enumeration:

0 : 0P5_STOP

0.5 stop bit.

1 : 1_STOP

1 stop bit.

2 : 1P5_STOP

1.5 stop bits.

3 : 2_STOP

2 stop bits.

End of enumeration elements list.

RPARMD : Receiver Parity Mode.
bits : 5 - 6 (2 bit)

Enumeration:

0 : ODD

Odd Parity.

1 : EVEN

Even Parity.

2 : MARK

Set (Parity = 1).

3 : SPACE

Clear (Parity = 0).

End of enumeration elements list.

RDATLN : Receiver Data Length.
bits : 8 - 10 (3 bit)

Enumeration:

0 : 5_BITS

5 bits.

1 : 6_BITS

6 bits.

2 : 7_BITS

7 bits.

3 : 8_BITS

8 bits.

4 : 9_BITS_STORED

9 bits. The 9th bit is stored in the FIFO (normal mode).

5 : 9_BITS_MATCH

9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD).

End of enumeration elements list.

RSCEN : Receiver Smartcard Parity Response Enable.
bits : 12 - 12 (1 bit)

Enumeration:

0 : DISABLED

The receiver does not send a Smartcard parity error response.

1 : ENABLED

The receiver sends a Smartcard parity response.

End of enumeration elements list.

RIRDAEN : Receiver IrDA Enable.
bits : 13 - 13 (1 bit)

Enumeration:

0 : DISABLED

The receiver does not operate in IrDA mode.

1 : ENABLED

The receiver operates in IrDA mode.

End of enumeration elements list.

RINVEN : Receiver Invert Enable.
bits : 14 - 14 (1 bit)

Enumeration:

0 : DISABLED

Do not invert the RX pin signals (the RX idle state is high).

1 : ENABLED

Invert the RX pin signals (the RX idle state is low).

End of enumeration elements list.

RSYNCEN : Receiver Synchronous Mode Enable.
bits : 15 - 15 (1 bit)

Enumeration:

0 : DISABLED

The receiver operates in asynchronous mode.

1 : ENABLED

The receiver operates in synchronous mode.

End of enumeration elements list.

TSTRTEN : Transmitter Start Enable.
bits : 16 - 16 (1 bit)

Enumeration:

0 : DISABLED

Do not generate a start bit during transmissions.

1 : ENABLED

Generate a start bit during transmissions.

End of enumeration elements list.

TPAREN : Transmitter Parity Enable.
bits : 17 - 17 (1 bit)

Enumeration:

0 : DISABLED

Do not send a parity bit during transmissions.

1 : ENABLED

Send a parity bit during transmissions.

End of enumeration elements list.

TSTPEN : Transmitter Stop Enable.
bits : 18 - 18 (1 bit)

Enumeration:

0 : DISABLED

Do not send stop bits during transmissions.

1 : ENABLED

Send stop bits during transmissions.

End of enumeration elements list.

TSTPMD : Transmitter Stop Mode.
bits : 19 - 20 (2 bit)

Enumeration:

0 : 0P5_STOP

0.5 stop bit.

1 : 1_STOP

1 stop bit.

2 : 1P5_STOP

1.5 stop bits.

3 : 2_STOP

2 stop bits.

End of enumeration elements list.

TPARMD : Transmitter Parity Mode.
bits : 21 - 22 (2 bit)

Enumeration:

0 : ODD

Odd Parity.

1 : EVEN

Even Parity.

2 : MARK

Set (Parity = 1).

3 : SPACE

Clear (Parity = 0).

End of enumeration elements list.

TDATLN : Transmitter Data Length.
bits : 24 - 26 (3 bit)

Enumeration:

0 : 5_BITS

5 bits.

1 : 6_BITS

6 bits.

2 : 7_BITS

7 bits.

3 : 8_BITS

8 bits.

4 : 9_BITS_FIFO

9 bits. The 9th bit is taken from the FIFO data (normal mode).

5 : 9_BITS_TBIT

9 bits. The 9th bit is set by the value of TBIT (fixed mode).

End of enumeration elements list.

TSCEN : Transmitter Smartcard Parity Response Enable.
bits : 28 - 28 (1 bit)

Enumeration:

0 : DISABLED

The transmitter does not check for a Smartcard parity error response.

1 : ENABLED

The transmitter checks for a Smartcard parity error response.

End of enumeration elements list.

TIRDAEN : Transmitter IrDA Enable.
bits : 29 - 29 (1 bit)

Enumeration:

0 : DISABLED

Disable IrDA transmit mode.

1 : ENABLED

Enable IrDA transmit mode.

End of enumeration elements list.

TINVEN : Transmitter Invert Enable.
bits : 30 - 30 (1 bit)

Enumeration:

0 : DISABLED

Do not invert the TX pin signals (the TX idle state is high).

1 : ENABLED

Invert the TX pin signals (the TX idle state is low).

End of enumeration elements list.

TSYNCEN : Transmitter Synchronous Mode Enable.
bits : 31 - 31 (1 bit)

Enumeration:

0 : DISABLED

The transmitter operates in asynchronous mode.

1 : ENABLED

The transmitter operates in synchronous mode.

End of enumeration elements list.


MODE

Module Mode Select
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGMD LBMD STPSTCLK STRTSTCLK ISTCLK DUPLEXMD CLKIDLE CLKESEL ITSEN OPMD

DBGMD : USART Debug Mode.
bits : 16 - 16 (1 bit)

Enumeration:

0 : RUN

The USART module will continue to operate while the core is halted in debug mode.

1 : HALT

A debug breakpoint will cause the USART module to halt. Any active transmissions and receptions will complete first.

End of enumeration elements list.

LBMD : Loop Back Mode.
bits : 18 - 19 (2 bit)

Enumeration:

0 : DISABLED

Loop back is disabled and the TX and RX signals are connected to the corresponding external pins.

1 : RXONLY

Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device.

2 : TXONLY

Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX.

3 : BOTH

Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX.

End of enumeration elements list.

STPSTCLK : Stop State Clock Control.
bits : 21 - 21 (1 bit)

Enumeration:

0 : DISABLED

When the USART is a clock master, the clock is not generated during stop bits.

1 : ENABLED

When the USART is a clock master, the clock is generated during stop bits.

End of enumeration elements list.

STRTSTCLK : Start State Clock Control.
bits : 22 - 22 (1 bit)

Enumeration:

0 : DISABLED

When the USART is a clock master, the clock is held idle during a start bit.

1 : ENABLED

When the USART is a clock master, the clock is generated during a start bit.

End of enumeration elements list.

ISTCLK : Idle Clock Control.
bits : 23 - 23 (1 bit)

Enumeration:

0 : DISABLED

When the USART is a clock master and CLKESEL is not equal to CLKIDLE, the clock is held idle between transmissions. When the USART is a clock master and CLKESEL equals CLKIDEL, the clock will still be generated between transmissions. When the USART is a clock slave, the USART will begin transmissions without waiting for the next clock edge.

1 : ENABLED

When the USART is a clock master, the clock is generated between transmissions or receptions. When the USART is a clock slave, the USART will wait until the next clock edge before transmitting.

End of enumeration elements list.

DUPLEXMD : Duplex Mode.
bits : 27 - 27 (1 bit)

Enumeration:

0 : FULL_DUPLEX

Full-duplex mode. The transmitter and receiver can operate simultaneously.

1 : HALF_DUPLEX

Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active.

End of enumeration elements list.

CLKIDLE : Clock Idle State.
bits : 28 - 28 (1 bit)

Enumeration:

0 : IDLE_LOW

The synchronous clock is low when idle.

1 : IDLE_HIGH

The synchronous clock is high when idle.

End of enumeration elements list.

CLKESEL : Clock Edge Select.
bits : 29 - 29 (1 bit)

Enumeration:

0 : FALLING

The clock falls in the middle of each bit.

1 : RISING

The clock rises in the middle of each bit.

End of enumeration elements list.

ITSEN : Idle TX/UCLK Tristate Enable.
bits : 30 - 30 (1 bit)

Enumeration:

0 : DISABLED

The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle.

1 : ENABLED

The TX pin is tristated when idle. If ISTCLK is cleared to 0 and the transmitter is configured in synchronous master mode, the UCLK pin will also be tristated when idle.

End of enumeration elements list.

OPMD : Operational Mode.
bits : 31 - 31 (1 bit)

Enumeration:

0 : SLAVE

The USART operates as a slave.

1 : MASTER

The USART operates as a master.

End of enumeration elements list.


FLOWCN

Flow Control
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLOWCN FLOWCN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTS RX RTSINVEN RTSTH RTSEN CTS TX UCLK CTSINVEN CTSEN TIRDAPW

RTS : RTS State.
bits : 0 - 0 (1 bit)

Enumeration:

0 : LOW

RTS pin (before optional inversion) is driven low.

1 : HIGH

RTS pin (before optional inversion) is driven high.

End of enumeration elements list.

RX : RX Pin Status.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : LOW

RX pin (after optional inversion) is low.

1 : HIGH

RX pin (after optional inversion) is high.

End of enumeration elements list.

RTSINVEN : RTS Invert Enable.
bits : 5 - 5 (1 bit)

Enumeration:

0 : DISABLED

The USART does not invert the RTS signal before driving the pin.

1 : ENABLED

The USART inverts the RTS signal driving the pin.

End of enumeration elements list.

RTSTH : RTS Threshold Control.
bits : 6 - 6 (1 bit)

Enumeration:

0 : FULL

RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored.

1 : ONE_BYTE_FREE

RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received.

End of enumeration elements list.

RTSEN : RTS Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : DISABLED

The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0).

1 : ENABLED

Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise.

End of enumeration elements list.

CTS : CTS State.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

0 : LOW

Indicates the CTS pin state (after optional inversion) is low.

1 : HIGH

Indicates the CTS pin state (after optional inversion) is high.

End of enumeration elements list.

TX : TX State.
bits : 17 - 17 (1 bit)

Enumeration:

0 : LOW

The TX pin (before optional inversion) is low.

1 : HIGH

The TX pin (before optional inversion) is high.

End of enumeration elements list.

UCLK : UCLK State.
bits : 18 - 18 (1 bit)

Enumeration:

0 : LOW

The UCLK pin is low.

1 : HIGH

The UCLK pin is high.

End of enumeration elements list.

CTSINVEN : CTS Invert Enable.
bits : 21 - 21 (1 bit)

Enumeration:

0 : DISABLED

The USART does not invert CTS.

1 : ENABLED

The USART inverts CTS.

End of enumeration elements list.

CTSEN : CTS Enable.
bits : 23 - 23 (1 bit)

Enumeration:

0 : DISABLED

The CTS pin state does not affect transmissions.

1 : ENABLED

Transmissions will begin only if the CTS pin (after optional inversion) is low.

End of enumeration elements list.

TIRDAPW : Transmit IrDA Pulse Width.
bits : 28 - 29 (2 bit)

Enumeration:

0 : 1_16TH

The IrDA pulse width is 1/16th of a bit period.

1 : 1_8TH

The IrDA pulse width is 1/8th of a bit period.

2 : 3_16TH

The IrDA pulse width is 3/16th of a bit period.

3 : 1_4TH

The IrDA pulse width is 1/4th of a bit period.

End of enumeration elements list.


CONTROL

Module Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFRMERI RPARERI ROREI RDREQI RERIEN RDREQIEN MATMD RABDEN RBUSYF RBIT ROSEN RINH REN TSCERI TUREI TDREQI TCPTI TCPTTH TERIEN TDREQIEN TCPTIEN TBUSYF TBIT TINH TEN

RFRMERI : Receive Frame Error Interrupt Flag.
bits : 0 - 0 (1 bit)

Enumeration:

0 : NOT_SET

Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt.

1 : SET

Read: A frame error occurred. Write: Force a frame error interrupt.

End of enumeration elements list.

RPARERI : Receive Parity Error Interrupt Flag.
bits : 1 - 1 (1 bit)

Enumeration:

0 : NOT_SET

Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt.

1 : SET

Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt.

End of enumeration elements list.

ROREI : Receive Overrun Error Interrupt Flag.
bits : 2 - 2 (1 bit)

Enumeration:

0 : NOT_SET

Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt.

1 : SET

Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt.

End of enumeration elements list.

RDREQI : Receive Data Request Interrupt Flag.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

Fewer than RFTH FIFO slots are filled with data.

1 : SET

At least RFTH FIFO slots are filled with data.

End of enumeration elements list.

RERIEN : Receive Error Interrupt Enable.
bits : 5 - 5 (1 bit)

Enumeration:

0 : DISABLED

Disable the receive error interrupt.

1 : ENABLED

Enable the receive error interrupt. A receive error interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1.

End of enumeration elements list.

RDREQIEN : Receive Data Request Interrupt Enable.
bits : 6 - 6 (1 bit)

Enumeration:

0 : DISABLED

Disable the read data request interrupt.

1 : ENABLED

Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1.

End of enumeration elements list.

MATMD : Match Mode.
bits : 8 - 9 (2 bit)

Enumeration:

0 : OFF

Disable the match function.

1 : MCE

(MCE) Data whose last data bit equals RBIT is accepted and stored.

2 : FRAME

(Frame) A framing error is asserted if the last received bit matches RBIT.

3 : STORE

(Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting.

End of enumeration elements list.

RABDEN : Receiver Auto-Baud Enable.
bits : 10 - 10 (1 bit)

Enumeration:

0 : DISABLED

Disable receiver auto-baud.

1 : ENABLED

Enable receiver auto-baud.

End of enumeration elements list.

RBUSYF : Receiver Busy Flag.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

The USART receiver is idle.

1 : SET

The USART receiver is receiving data.

End of enumeration elements list.

RBIT : Last Receive Bit.
bits : 12 - 12 (1 bit)

Enumeration:

0 : NOT_SET

None

1 : SET

None

End of enumeration elements list.

ROSEN : Receiver One-Shot Enable.
bits : 13 - 13 (1 bit)

Enumeration:

0 : DISABLED

Disable one-shot receive mode.

1 : ENABLED

Enable one-shot receive mode.

End of enumeration elements list.

RINH : Receiver Inhibit.
bits : 14 - 14 (1 bit)

Enumeration:

0 : INACTIVE

The receiver operates normally.

1 : ACTIVE

RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that.

End of enumeration elements list.

REN : Receiver Enable.
bits : 15 - 15 (1 bit)

Enumeration:

0 : DISABLED

Disable the receiver. The receiver can receive one data transaction only if ROSEN is set.

1 : ENABLED

Enable the receiver.

End of enumeration elements list.

TSCERI : Smartcard Parity Error Interrupt Flag.
bits : 16 - 16 (1 bit)

Enumeration:

0 : NOT_SET

Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt.

1 : SET

Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt.

End of enumeration elements list.

TUREI : Transmit Underrun Error Interrupt Flag.
bits : 17 - 17 (1 bit)

Enumeration:

0 : NOT_SET

Read: A transmitter underrun has not occurred since TUREI was last cleared. Write: Clear the interrupt.

1 : SET

Read: A transmitter underrun occurred. Write: Force a transmitter underrun interrupt.

End of enumeration elements list.

TDREQI : Transmit Data Request Interrupt Flag.
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

The transmitter is not requesting more FIFO data.

1 : SET

The transmitter is requesting more FIFO data.

End of enumeration elements list.

TCPTI : Transmit Complete Interrupt Flag.
bits : 19 - 19 (1 bit)

Enumeration:

0 : NOT_SET

Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt.

1 : SET

Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt.

End of enumeration elements list.

TCPTTH : Transmit Complete Threshold.
bits : 20 - 20 (1 bit)

Enumeration:

0 : SET_ON_TX

A transmit is completed (TCPTI = 1) at the end of each transmission.

1 : SET_ON_EMPTY

A transmit is completed (TCPTI = 1) only at the end of a transmission when no more data is available to transmit.

End of enumeration elements list.

TERIEN : Transmit Error Interrupt Enable.
bits : 21 - 21 (1 bit)

Enumeration:

0 : DISABLED

Disable the transmit error interrupt.

1 : ENABLED

Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1.

End of enumeration elements list.

TDREQIEN : Transmit Data Request Interrupt Enable.
bits : 22 - 22 (1 bit)

Enumeration:

0 : DISABLED

Disable the transmit data request interrupt.

1 : ENABLED

Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1.

End of enumeration elements list.

TCPTIEN : Transmit Complete Interrupt Enable.
bits : 23 - 23 (1 bit)

Enumeration:

0 : DISABLED

Disable the transmit complete interrupt.

1 : ENABLED

Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1.

End of enumeration elements list.

TBUSYF : Transmitter Busy Flag.
bits : 27 - 27 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

The USART transmitter is idle.

1 : SET

The USART transmitter is active and transmitting.

End of enumeration elements list.

TBIT : Last Transmit Bit.
bits : 28 - 28 (1 bit)

Enumeration:

0 : NOT_SET

None

1 : SET

None

End of enumeration elements list.

TINH : Transmit Inhibit.
bits : 30 - 30 (1 bit)

Enumeration:

0 : INACTIVE

The transmitter operates normally.

1 : ACTIVE

Transmissions are inhibited. The transmitter will stall after any current transmission is complete.

End of enumeration elements list.

TEN : Transmitter Enable.
bits : 31 - 31 (1 bit)

Enumeration:

0 : DISABLED

Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO.

1 : ENABLED

Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO.

End of enumeration elements list.


IPDELAY

Inter-Packet Delay
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPDELAY IPDELAY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPDELAY

IPDELAY : Inter-Packet Delay.
bits : 16 - 23 (8 bit)


BAUDRATE

Transmit and Receive Baud Rate
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BAUDRATE BAUDRATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBAUD TBAUD

RBAUD : Receiver Baud Rate Control.
bits : 0 - 15 (16 bit)

TBAUD : Transmitter Baud Rate Control.
bits : 16 - 31 (16 bit)


FIFOCN

FIFO Control
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOCN FIFOCN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCNT RFTH RDMAEN RFIFOFL RFERI RSRFULLF TCNT TFTH TDMAEN TFIFOFL TFERI TSRFULLF

RCNT : Receive FIFO Count.
bits : 0 - 2 (3 bit)
access : read-only

RFTH : Receive FIFO Threshold.
bits : 4 - 5 (2 bit)

Enumeration:

0 : ONE

A DMA request or read data request interrupt (RDREQI) is asserted when >= 1 FIFO slot is full.

1 : TWO

A DMA request or read data request interrupt (RDREQI) is asserted when >= 2 FIFO slots are full.

2 : FOUR

A DMA request or read data request interrupt (RDREQ) is asserted when >= 4 FIFO slots are full.

End of enumeration elements list.

RDMAEN : Receiver DMA Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : DISABLED

Disable receive FIFO DMA requests.

1 : ENABLED

Enable receive FIFO DMA requests.

End of enumeration elements list.

RFIFOFL : Receive FIFO Flush.
bits : 8 - 8 (1 bit)

Enumeration:

1 : SET

Flush the contents of the receive FIFO and any data in the receive shift register.

End of enumeration elements list.

RFERI : Receive FIFO Error Interrupt Flag.
bits : 9 - 9 (1 bit)

Enumeration:

0 : NOT_SET

A receive FIFO error has not occurred since RFERI was last cleared.

1 : SET

A receive FIFO error occurred.

End of enumeration elements list.

RSRFULLF : Receive Shift Register Full Flag.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

The receive data shift register is not full.

1 : SET

The receive data shift register is full.

End of enumeration elements list.

TCNT : Transmit FIFO Count.
bits : 16 - 18 (3 bit)
access : read-only

TFTH : Transmit FIFO Threshold.
bits : 20 - 21 (2 bit)

Enumeration:

0 : ONE

A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO slot is empty.

1 : TWO

A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO slots are empty.

2 : FOUR

A DMA request or transmit data request interrupt (TDREQ) is asserted when >= 4 FIFO slots are empty.

End of enumeration elements list.

TDMAEN : Transmitter DMA Enable.
bits : 23 - 23 (1 bit)

Enumeration:

0 : DISABLED

Disable transmit FIFO DMA requests.

1 : ENABLED

Enable transmit FIFO DMA requests.

End of enumeration elements list.

TFIFOFL : Transmit FIFO Flush.
bits : 24 - 24 (1 bit)

Enumeration:

1 : SET

Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed.

End of enumeration elements list.

TFERI : Transmit FIFO Error Interrupt Flag.
bits : 25 - 25 (1 bit)

Enumeration:

0 : NOT_SET

A transmit FIFO error has not occurred since TFERI was last cleared.

1 : SET

A transmit FIFO error occurred.

End of enumeration elements list.

TSRFULLF : Transmit Shift Register Full Flag.
bits : 26 - 26 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

The transmit shift register is not full.

1 : SET

The transmit shift register is full.

End of enumeration elements list.


DATA

FIFO Input/Output Data
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : FIFO Data.
bits : 0 - 31 (32 bit)



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