\n

WDTIMER_0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONTROL

STATUS

THRESHOLD

WDTKEY


CONTROL

Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EWIEN DBGMD

EWIEN : Early Warning Interrupt Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : DISABLED

Disable the early warning interrupt (EWI).

1 : ENABLED

Enable the early warning interrupt (EWI).

End of enumeration elements list.

DBGMD : Watchdog Timer Debug Mode.
bits : 1 - 1 (1 bit)

Enumeration:

0 : RUN

The WDTIMER module will continue to operate while the core is halted in debug mode.

1 : HALT

A debug breakpoint will cause the WDTIMER module to halt.

End of enumeration elements list.


STATUS

Module Status
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYSTS PRIVSTS EWI RTHF UPDSTS

KEYSTS : Key Status.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : IDLE

No keys have been processed by the interface.

1 : READY

The attention key has been received and the module is awaiting a command.

End of enumeration elements list.

PRIVSTS : Register Access Status.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : READ_ONLY

The watchdog timer registers are currently read-only.

1 : READ_WRITE

A write transaction can be performed on the module registers.

End of enumeration elements list.

EWI : Early Warning Interrupt Flag.
bits : 2 - 2 (1 bit)

Enumeration:

0 : NOT_SET

Read: An early warning match did not occur. Write: Clear the early warning interrupt.

1 : SET

Read: An early warning match occurred and the interrupt is pending. Write: Force a watchdog timer early warning interrupt to occur.

End of enumeration elements list.

RTHF : Reset Threshold Flag.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : LT

The counter is currently less than the reset threshold (RTH) value.

1 : GTE

The counter is currently greater than or equal to the reset threshold (RTH) value.

End of enumeration elements list.

UPDSTS : Watchdog Timer Threshold Update Status.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : IDLE

An update completed or is not pending. The EWTH and RTH fields can be written.

1 : UPDATING

An update of the threshold register is occurring. The EWTH and RTH fields should not be modified until hardware clears UPDSTS to 0.

End of enumeration elements list.


THRESHOLD

Threshold Values
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

THRESHOLD THRESHOLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EWTH RTH

EWTH : Early Warning Threshold.
bits : 0 - 15 (16 bit)

RTH : Reset Threshold.
bits : 16 - 31 (16 bit)


WDTKEY

Module Key
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTKEY WDTKEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : Watchdog Timer Key.
bits : 0 - 7 (8 bit)
access : write-only

Enumeration:

165 : ATTN

Attention key to start the command sequence.

204 : RESET

Reset the watchdog timer.

221 : DISABLE

Disable the watchdog timer.

238 : START

Start the watchdog timer.

241 : WRITE

Allow one write access to the module registers.

255 : LOCK

Lock the module from any other writes until the next system reset.

End of enumeration elements list.



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