Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHBSEL : AHB Clock Source Select.
bits : 0 - 2 (3 bit)
Enumeration:
0 : LPOSC0
AHB clock source is the Low-Power Oscillator.
1 : LFOSC0
AHB clock source is the Low-Frequency Oscillator.
2 : RTC0TCLK
AHB clock source is the RTC0TCLK signal.
3 : EXTOSC0
AHB clock source is the External Oscillator.
4 : VIORFCLK
AHB clock source is the VIORFCLK input pin.
5 : PLL0OSC
AHB clock source is the PLL.
6 : LPOSC0_DIV
AHB clock source is a divided version of the Low-Power Oscillator.
End of enumeration elements list.
AHBDIV : AHB Clock Divider.
bits : 8 - 10 (3 bit)
Enumeration:
0 : DIV1
AHB clock divided by 1.
1 : DIV2
AHB clock divided by 2.
2 : DIV4
AHB clock divided by 4.
3 : DIV8
AHB clock divided by 8.
4 : DIV16
AHB clock divided by 16.
5 : DIV32
AHB clock divided by 32.
6 : DIV64
AHB clock divided by 64.
7 : DIV128
AHB clock divided by 128.
End of enumeration elements list.
APBDIV : APB Clock Divider.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DIV1
APB clock is the same as the AHB clock (divided by 1).
1 : DIV2
APB clock is the AHB clock divided by 2.
End of enumeration elements list.
EXTESEL : External Clock Edge Select.
bits : 28 - 28 (1 bit)
Enumeration:
0 : BOTH_EDGES
External clock generated by both rising and falling edges of the external oscillator.
1 : RISING_ONLY
External clock generated by only rising edges of the external oscillator.
End of enumeration elements list.
OBUSYF : Oscillators Busy Flag.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
AHB and APB oscillators are not busy.
1 : SET
AHB and APB oscillators are busy and the AHBSEL, AHBDIV, and APBDIV fields should not be modified.
End of enumeration elements list.
VIORFCLKEN : VIORF Clock Enable.
bits : 30 - 30 (1 bit)
Enumeration:
0 : DISABLED
Disable the VIORFCLK input.
1 : ENABLED
Enable the VIORFCLK input.
End of enumeration elements list.
EXTOSCEN : External Clock Input Enable.
bits : 31 - 31 (1 bit)
Enumeration:
0 : DISABLED
Disable the EXTOSC input.
1 : ENABLED
Enable the EXTOSC input.
End of enumeration elements list.
AHB Clock Gate
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMCEN : RAM Clock Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the AHB clock to the RAM.
1 : ENABLED
Enable the AHB clock to the RAM.
End of enumeration elements list.
DMACEN : DMA Clock Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable the AHB clock to the DMA Controller.
1 : ENABLED
Enable the AHB clock to the DMA Controller.
End of enumeration elements list.
FLASHCEN : Flash Clock Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable the AHB clock to the Flash.
1 : ENABLED
Enable the AHB clock to the Flash.
End of enumeration elements list.
DTM0EN : DTM0 Clock Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
Disable the AHB clock to Data Transfer Manager 0 (DTM0).
1 : ENABLED
Enable the AHB clock to Data Transfer Manager 0 (DTM0).
End of enumeration elements list.
DTM1EN : DTM1 Clock Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
Disable the AHB clock to Data Transfer Manager 1 (DTM1).
1 : ENABLED
Enable the AHB clock to Data Transfer Manager 1 (DTM1).
End of enumeration elements list.
DTM2EN : DTM2 Clock Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DISABLED
Disable the AHB clock to Data Transfer Manager 2 (DTM2).
1 : ENABLED
Enable the AHB clock to Data Transfer Manager 2 (DTM2).
End of enumeration elements list.
APB Clock Gate 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLCTRLCEN : Flash Controller Clock Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the Flash Controller Module (FLASHCTRL0).
1 : ENABLED
Enable the APB clock to the Flash Controller Module (FLASHCTRL0).
End of enumeration elements list.
PB0CEN : Port Bank Clock Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the Port Bank Modules.
1 : ENABLED
Enable the APB clock to the Port Bank Modules.
End of enumeration elements list.
USART0CEN : USART0 Clock Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the USART0 Module.
1 : ENABLED
Enable the APB clock to the USART0 Module.
End of enumeration elements list.
UART0CEN : UART0 Clock Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the UART0 Module.
1 : ENABLED
Enable the APB clock to the UART0 Module.
End of enumeration elements list.
SPI0CEN : SPI0 Clock Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the SPI0 Module.
1 : ENABLED
Enable the APB clock to the SPI0 Module.
End of enumeration elements list.
SPI1CEN : SPI1 Clock Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the SPI1 Module.
1 : ENABLED
Enable the APB clock to the SPI1 Module.
End of enumeration elements list.
I2C0CEN : I2C0 Clock Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the I2C0 Module.
1 : ENABLED
Enable the APB clock to the I2C0 Module.
End of enumeration elements list.
EPCA0CEN : EPCA0 Clock Enable.
bits : 7 - 7 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the EPCA0 Module.
1 : ENABLED
Enable the APB clock to the EPCA0 Module.
End of enumeration elements list.
TIMER0CEN : TIMER0 Clock Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the TIMER0 Module.
1 : ENABLED
Enable the APB clock to the TIMER0 Module.
End of enumeration elements list.
TIMER1CEN : TIMER1 Clock Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the TIMER1 Module.
1 : ENABLED
Enable the APB clock to the TIMER1 Module.
End of enumeration elements list.
TIMER2CEN : TIMER2 Clock Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the TIMER2 Module.
1 : ENABLED
Enable the APB clock to the TIMER2 Module.
End of enumeration elements list.
ADC0CEN : SARADC0 Clock Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the SARADC0 Module.
1 : ENABLED
Enable the APB clock to the SARADC0 Module.
End of enumeration elements list.
CMP0CEN : CMP0 Clock Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the Comparator 0 Module.
1 : ENABLED
Enable the APB clock to the Comparator 0 Module.
End of enumeration elements list.
CMP1CEN : CMP1 Clock Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the Comparator 1 Module.
1 : ENABLED
Enable the APB clock to the Comparator 1 Module.
End of enumeration elements list.
AES0CEN : AES0 Clock Enable.
bits : 14 - 14 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the AES0 Module.
1 : ENABLED
Enable the APB clock to the AES0 Module.
End of enumeration elements list.
CRC0CEN : CRC0 Clock Enable.
bits : 15 - 15 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the CRC0 Module.
1 : ENABLED
Enable the APB clock to the CRC0 Module.
End of enumeration elements list.
IDAC0CEN : IDAC0 Clock Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the IDAC0 Module.
1 : ENABLED
Enable the APB clock to the IDAC0 Module.
End of enumeration elements list.
LPT0CEN : LPT0 Clock Enable.
bits : 17 - 17 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the LPTIMER0 Module.
1 : ENABLED
Enable the APB clock to the LPTIMER0 Module.
End of enumeration elements list.
ACCTR0CEN : ACCTR0 Enable.
bits : 18 - 18 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the ACCTR0 Module.
1 : ENABLED
Enable the APB clock to the ACCTR0 Module.
End of enumeration elements list.
DTM0CEN : DTM0 Clock Enable.
bits : 19 - 19 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the DTM0 Register interface.
1 : ENABLED
Enable the APB clock to the DTM0 Register interface.
End of enumeration elements list.
DTM1CEN : DTM1 Clock Enable.
bits : 20 - 20 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the DTM1 Register interface.
1 : ENABLED
Enable the APB clock to the DTM1 Register interface.
End of enumeration elements list.
DTM2CEN : DTM2 Clock Enable.
bits : 21 - 21 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the DTM2 Register interface.
1 : ENABLED
Enable the APB clock to the DTM2 Register interface.
End of enumeration elements list.
LCD0CEN : LCD0 Clock Enable.
bits : 22 - 22 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the LCD0 Module.
1 : ENABLED
Enable the APB clock to the LCD0 Module.
End of enumeration elements list.
DCDC0CEN : DCDC0 Clock Enable.
bits : 23 - 23 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the DCDC0 Module.
1 : ENABLED
Enable the APB clock to the DCDC0 Module.
End of enumeration elements list.
ENCDEC0CEN : ENCDEC0 Clock Enable.
bits : 24 - 24 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the ENCDEC0 Module.
1 : ENABLED
Enable the APB clock to the ENCDEC0 Module.
End of enumeration elements list.
PLL0CEN : PLL0 Clock Enable.
bits : 25 - 25 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the PLL0 registers.
1 : ENABLED
Enable the APB clock to the PLL0 registers.
End of enumeration elements list.
APB Clock Gate 1
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MISC0CEN : Miscellaneous 0 Clock Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC modules.
1 : ENABLED
Enable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC modules.
End of enumeration elements list.
MISC1CEN : Miscellaneous 1 Clock Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable the APB clock to the Watchdog Timer (WDTIMER0) and DMA Crossbar (DMAXBAR0) modules.
1 : ENABLED
Enable the APB clock to the Watchdog Timer (WDTIMER0) and DMA Crossbar (DMAXBAR0) modules.
End of enumeration elements list.
Power Mode 3 Clock Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PM3CSEL : Power Mode 3 Fast-Wake Clock Source.
bits : 0 - 2 (3 bit)
Enumeration:
0 : LPOSC0_DIV
Power Mode 3 clock source is the Low-Power Oscillator.
1 : LFOSC0
Power Mode 3 clock source is the Low-Frequency Oscillator.
2 : RTC0TCLK
Power Mode 3 clock source is the RTC0TCLK signal.
3 : EXTOSC0
Power Mode 3 clock source is the External Oscillator.
4 : VIORFCLK
Power Mode 3 clock source is the VIORFCLK input pin.
5 : PLL0OSC
Power Mode 3 clock source is the PLL.
6 : LPOSC0
Power Mode 3 clock source is a divided version of the Low-Power Oscillator.
End of enumeration elements list.
PM3CEN : Power Mode 3 Fast-Wake Clock Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
Disable the core clock when in Power Mode 3.
1 : ENABLED
The core clock is enabled and runs off the clock selected by PM3CSEL in Power Mode 3.
End of enumeration elements list.
Configuration Options
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMSEL : Power Mode Select.
bits : 0 - 0 (1 bit)
Enumeration:
0 : PM8_DIS
Power Mode < PM8.
1 : PM8_EN
Power Mode = PM8.
End of enumeration elements list.
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