Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRDYIEN : Input Ready Interrupt Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the input ready interrupt.
1 : ENABLED
Enable the input ready interrupt.
End of enumeration elements list.
ORDYIEN : Output Ready Interrupt Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable the output ready interrupt.
1 : ENABLED
Enable the output ready interrupt.
End of enumeration elements list.
ERRIEN : Error Interrupt Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable the error interrupt.
1 : ENABLED
Enable the error interrupt.
End of enumeration elements list.
RESET : Module Reset.
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
1 : ACTIVE
Reset the module.
End of enumeration elements list.
MOSIZE : Manchester Output Size.
bits : 4 - 4 (1 bit)
Enumeration:
0 : SMALL
Manchester encode operations generate a half-word output, and decode operations generate a byte output.
1 : LARGE
Manchester encode operations generate a word output, and decode operations generate a half-word output.
End of enumeration elements list.
EDMD : Encode Decode Mode.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DECODE
Decode data written to DATAIN.
1 : ENCODE
Encode data written to DATAIN.
End of enumeration elements list.
OPMD : Operation Mode.
bits : 6 - 6 (1 bit)
Enumeration:
0 : MANCHESTER
The operation selected by EDMD uses Manchester mode.
1 : 3OUTOF6
The operation selected by EDMD uses Three-out-of-Six mode.
End of enumeration elements list.
BEN : Bypass Encoder/Decoder Operation Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Do not bypass ENCDEC operations.
1 : ENABLED
Bypass ENCDEC operations.
End of enumeration elements list.
DMAEN : DMA Mode Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Disable DMA mode.
1 : ENABLED
Enable DMA mode.
End of enumeration elements list.
DBGMD : Debug Mode.
bits : 10 - 10 (1 bit)
Enumeration:
0 : RUN
The ENCDEC module will continue to operate while the core is halted in debug mode.
1 : HALT
A debug breakpoint will cause the ENCDEC module to halt.
End of enumeration elements list.
OORDER : Output Order Mode.
bits : 12 - 13 (2 bit)
Enumeration:
0 : NO_CHANGE
The module outputs data to DATAOUT in the same order as it was processed (input: B3 B2 B1 B0, output: B3 B2 B1 B0).
1 : HALF_WORD
The module flips the data in half-words before outputting to DATAOUT (input: B3 B2 B1 B0, output: B2 B3 B0 B1).
2 : WORD
The module flips the data in words before outputting to DATAOUT (input: B3 B2 B1 B0, output: B0 B1 B2 B3).
3 : LOWER_THREE_BYTES
The module flips the lower three bytes before outputting to DATAOUT (input: B3 B2 B1 B0, output: B3 B0 B1 B2).
End of enumeration elements list.
IORDER : Input Order Mode.
bits : 14 - 15 (2 bit)
Enumeration:
0 : NO_CHANGE
Data written to DATAIN is processed in the order written (input: B3 B2 B1 B0, output: B3 B2 B1 B0).
1 : HALF_WORD
The module flips the DATAIN input data in half-words (input: B2 B3 B0 B1, output: B3 B2 B1 B0).
2 : WORD
The module flips the DATAIN input data in words (input: B0 B1 B2 B3, output: B3 B2 B1 B0).
3 : LOWER_THREE_BYTES
The module flips the lower three bytes of the DATAIN input data (input: B3 B0 B1 B2, output: B3 B2 B1 B0).
End of enumeration elements list.
Module Status
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRDYI : Input Ready Interrupt Flag.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The input FIFO is not ready for new data.
1 : SET
Firmware can write new input data to DATAIN.
End of enumeration elements list.
ORDYI : Output Ready Interrupt Flag.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The output data is not ready.
1 : SET
The output data is ready to be read by firmware.
End of enumeration elements list.
DERRI : Data Error Interrupt Flag.
bits : 2 - 2 (1 bit)
Enumeration:
0 : NOT_SET
None
1 : SET
None
End of enumeration elements list.
DURI : Data Underrun Interrupt Flag.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NOT_SET
No output data FIFO underrun.
1 : SET
An output data FIFO underrun has occurred.
End of enumeration elements list.
DORI : Data Overrun Interrupt Flag.
bits : 4 - 4 (1 bit)
Enumeration:
0 : NOT_SET
No input data FIFO overrun.
1 : SET
An input data FIFO overrun has occurred.
End of enumeration elements list.
Data Input
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAIN : Data Input.
bits : 0 - 31 (32 bit)
Data Output
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAOUT : Data Output.
bits : 0 - 31 (32 bit)
Data Output Complement
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAOUTC : Data Output Complement.
bits : 0 - 31 (32 bit)
access : read-only
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