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LPTIMER_0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONTROL

COUNT

THRESHOLD

STATUS


CONTROL

Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD EXTSEL TMRSET TMRCAP HSMDEN CMP0EN CMP1EN OUTEN OVFIEN CMP0IEN OVFOEN CMP0OEN CMP1IEN CMP1OEN OUTINVEN CMP0RSTEN CMP1RSTEN MCLKEN DBGMD RUN

CMD : Count Mode.
bits : 0 - 1 (2 bit)

Enumeration:

0 : FREE

The timer is free running mode on the RTC timer clock (RTC0TCLK).

1 : RISING_EDGE

The timer is incremented on the rising edges of the selected external trigger (LPTnTx).

2 : FALLING_EDGE

The timer is incremented on the falling edges of the selected external trigger (LPTnTx).

3 : ANY_EDGE

The timer is incremented on both edges of the selected external trigger (LPTnTx).

End of enumeration elements list.

EXTSEL : External Trigger Source Select.
bits : 4 - 7 (4 bit)

Enumeration:

0 : LPTNT0

Select external trigger LPTnT0.

1 : LPTNT1

Select external trigger LPTnT1.

2 : LPTNT2

Select external trigger LPTnT2.

3 : LPTNT3

Select external trigger LPTnT3.

4 : LPTNT4

Select external trigger LPTnT4.

5 : LPTNT5

Select external trigger LPTnT5.

6 : LPTNT6

Select external trigger LPTnT6.

7 : LPTNT7

Select external trigger LPTnT7.

8 : LPTNT8

Select external trigger LPTnT8.

9 : LPTNT9

Select external trigger LPTnT9.

10 : LPTNT10

Select external trigger LPTnT10.

11 : LPTNT11

Select external trigger LPTnT11.

12 : LPTNT12

Select external trigger LPTnT12.

13 : LPTNT13

Select external trigger LPTnT13.

14 : LPTNT14

Select external trigger LPTnT14.

15 : LPTNT15

Select external trigger LPTnT15.

End of enumeration elements list.

TMRSET : Timer Set.
bits : 8 - 8 (1 bit)

Enumeration:

1 : SET

Writing a 1 to TMRSET initiates a copy of the value from the COUNT register into the internal timer register. This field is automatically cleared by hardware when the copy is complete and does not need to be cleared by software.

End of enumeration elements list.

TMRCAP : Timer Capture.
bits : 9 - 9 (1 bit)

Enumeration:

1 : SET

Writing a 1 to TMRCAP initiates a read of internal timer register into the COUNT register. This field is automatically cleared by hardware when the operation completes and does not need to be cleared by software.

End of enumeration elements list.

HSMDEN : High Speed Timer Access Mode Enable.
bits : 10 - 10 (1 bit)

Enumeration:

0 : DISABLED

Disable high speed timer access mode.

1 : ENABLED

Enable high speed timer access mode.

End of enumeration elements list.

CMP0EN : Timer Compare 0 Threshold Enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : DISABLED

None

1 : ENABLED

None

End of enumeration elements list.

CMP1EN : Timer Compare 1 Threshold Enable.
bits : 12 - 12 (1 bit)

Enumeration:

0 : DISABLED

None

1 : ENABLED

None

End of enumeration elements list.

OUTEN : Output Enable.
bits : 13 - 13 (1 bit)

Enumeration:

0 : DISABLED

Disable the LPTIMER0 output.

1 : ENABLED

Enable the LPTIMER0 output.

End of enumeration elements list.

OVFIEN : Timer Overflow Interrupt Enable.
bits : 16 - 16 (1 bit)

Enumeration:

0 : DISABLED

Disable the timer overflow interrupt.

1 : ENABLED

Enable the timer overflow interrupt.

End of enumeration elements list.

CMP0IEN : Timer Compare 0 Event Interrupt Enable.
bits : 17 - 17 (1 bit)

Enumeration:

0 : DISABLED

Disable the timer compare 0 event interrupt.

1 : ENABLED

Enable the timer compare 0 event interrupt.

End of enumeration elements list.

OVFOEN : Timer Overflow Output Enable.
bits : 18 - 18 (1 bit)

Enumeration:

0 : DISABLED

Timer overflows do not modify the Low Power Timer output.

1 : ENABLED

Timer overflows set the Low Power Timer output to 1.

End of enumeration elements list.

CMP0OEN : Timer Compare 0 Event Output Enable.
bits : 19 - 19 (1 bit)

Enumeration:

0 : DISABLED

Timer compare 0 events do not modify the Low Power Timer output.

1 : ENABLED

Timer compare 0 events clear the Low Power Timer output to 0.

End of enumeration elements list.

CMP1IEN : Timer Compare 1 Event Interrupt Enable.
bits : 20 - 20 (1 bit)

Enumeration:

0 : DISABLED

Disable the timer compare 1 event interrupt.

1 : ENABLED

Enable the timer compare 1 event interrupt.

End of enumeration elements list.

CMP1OEN : Timer Compare 1 Event Output Enable.
bits : 21 - 21 (1 bit)

Enumeration:

0 : DISABLED

Timer compare 1 events do not modify the Low Power Timer output.

1 : ENABLED

Timer compare 1 events set the Low Power Timer output to 1.

End of enumeration elements list.

OUTINVEN : Output Inversion Enable.
bits : 22 - 22 (1 bit)

Enumeration:

0 : DISABLED

Do not invert the LPTIMER0 output.

1 : ENABLED

Invert the LPTIMER0 output.

End of enumeration elements list.

CMP0RSTEN : Timer Compare 0 Event Reset Enable.
bits : 24 - 24 (1 bit)

Enumeration:

0 : DISABLED

Timer compare 0 events do not reset the timer.

1 : ENABLED

Timer compare 0 events reset the timer.

End of enumeration elements list.

CMP1RSTEN : Timer Compare 1 Event Reset Enable.
bits : 25 - 25 (1 bit)

Enumeration:

0 : DISABLED

Timer compare 1 events do not reset the timer.

1 : ENABLED

Timer compare 1 events reset the timer.

End of enumeration elements list.

MCLKEN : Low Power Timer Module Clock Enable.
bits : 29 - 29 (1 bit)

Enumeration:

0 : DISABLED

Disable the clock to the Low Power Timer module.

1 : ENABLED

Enable the clock to the Low Power Timer module.

End of enumeration elements list.

DBGMD : Low Power Timer Debug Mode.
bits : 30 - 30 (1 bit)

Enumeration:

0 : RUN

The Low Power Timer module will continue to operate while the core is halted in debug mode.

1 : HALT

A debug breakpoint will cause the Low Power Timer module to halt.

End of enumeration elements list.

RUN : Timer Run Control and Compare Threshold Enable.
bits : 31 - 31 (1 bit)

Enumeration:

0 : STOP

Stop the timer and disable the compare threshold.

1 : START

Start the timer running and enable the compare threshold.

End of enumeration elements list.


COUNT

Timer Value
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER

TIMER : Timer Value.
bits : 0 - 15 (16 bit)


THRESHOLD

Threshold Values
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

THRESHOLD THRESHOLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPARE0 COMPARE1

COMPARE0 : Timer Compare 0 Threshold Value.
bits : 0 - 15 (16 bit)

COMPARE1 : Timer Compare 1 Threshold Value.
bits : 16 - 31 (16 bit)


STATUS

Module Status
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVFI CMP0I CMP1I

OVFI : Timer Overflow Interrupt Flag.
bits : 0 - 0 (1 bit)

Enumeration:

0 : NOT_SET

A timer overflow has not occurred.

1 : SET

A timer overflow occurred.

End of enumeration elements list.

CMP0I : Timer Compare 0 Event Interrupt Flag.
bits : 1 - 1 (1 bit)

Enumeration:

0 : NOT_SET

A timer compare 0 event has not occurred.

1 : SET

A timer compare 0 event occurred.

End of enumeration elements list.

CMP1I : Timer Compare 1 Event Interrupt Flag.
bits : 2 - 2 (1 bit)

Enumeration:

0 : NOT_SET

A timer compare 1 event has not occurred.

1 : SET

A timer compare 1 event occurred.

End of enumeration elements list.



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