Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTRTEN : Receiver Start Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Do not expect a start bit during receptions.
1 : ENABLED
Expect a start bit during receptions.
End of enumeration elements list.
RPAREN : Receiver Parity Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Do not expect a parity bit during receptions.
1 : ENABLED
Expect a parity bit during receptions.
End of enumeration elements list.
RSTPEN : Receiver Stop Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Do not expect stop bits during receptions.
1 : ENABLED
Expect stop bits during receptions.
End of enumeration elements list.
RSTPMD : Receiver Stop Mode.
bits : 3 - 4 (2 bit)
Enumeration:
0 : 0P5_STOP
0.5 stop bit.
1 : 1_STOP
1 stop bit.
2 : 1P5_STOP
1.5 stop bits.
3 : 2_STOP
2 stop bits.
End of enumeration elements list.
RPARMD : Receiver Parity Mode.
bits : 5 - 6 (2 bit)
Enumeration:
0 : ODD
Odd Parity.
1 : EVEN
Even Parity.
2 : MARK
Set (Parity = 1).
3 : SPACE
Clear (Parity = 0).
End of enumeration elements list.
RDATLN : Receiver Data Length.
bits : 8 - 10 (3 bit)
Enumeration:
0 : 5_BITS
5 bits.
1 : 6_BITS
6 bits.
2 : 7_BITS
7 bits.
3 : 8_BITS
8 bits.
4 : 9_BITS_STORED
9 bits. The 9th bit is stored in the FIFO (normal mode).
5 : 9_BITS_MATCH
9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD).
End of enumeration elements list.
RSCEN : Receiver Smartcard Parity Response Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
The receiver does not send a Smartcard parity error response.
1 : ENABLED
The receiver sends a Smartcard parity response.
End of enumeration elements list.
RIRDAEN : Receiver IrDA Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
The receiver does not operate in IrDA mode.
1 : ENABLED
The receiver operates in IrDA mode.
End of enumeration elements list.
RINVEN : Receiver Invert Enable.
bits : 14 - 14 (1 bit)
Enumeration:
0 : DISABLED
Do not invert the RX pin signals (the RX idle state is high).
1 : ENABLED
Invert the RX pin signals (the RX idle state is low).
End of enumeration elements list.
TSTRTEN : Transmitter Start Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
Do not generate a start bit during transmissions.
1 : ENABLED
Generate a start bit during transmissions.
End of enumeration elements list.
TPAREN : Transmitter Parity Enable.
bits : 17 - 17 (1 bit)
Enumeration:
0 : DISABLED
Do not send a parity bit during transmissions.
1 : ENABLED
Send a parity bit during transmissions.
End of enumeration elements list.
TSTPEN : Transmitter Stop Enable.
bits : 18 - 18 (1 bit)
Enumeration:
0 : DISABLED
Do not send stop bits during transmissions.
1 : ENABLED
Send stop bits during transmissions.
End of enumeration elements list.
TSTPMD : Transmitter Stop Mode.
bits : 19 - 20 (2 bit)
Enumeration:
0 : 0P5_STOP
0.5 stop bit.
1 : 1_STOP
1 stop bit.
2 : 1P5_STOP
1.5 stop bits.
3 : 2_STOP
2 stop bits.
End of enumeration elements list.
TPARMD : Transmitter Parity Mode.
bits : 21 - 22 (2 bit)
Enumeration:
0 : ODD
Odd Parity.
1 : EVEN
Even Parity.
2 : MARK
Set (Parity = 1).
3 : SPACE
Clear (Parity = 0).
End of enumeration elements list.
TDATLN : Transmitter Data Length.
bits : 24 - 26 (3 bit)
Enumeration:
0 : 5_BITS
5 bits.
1 : 6_BITS
6 bits.
2 : 7_BITS
7 bits.
3 : 8_BITS
8 bits.
4 : 9_BITS_FIFO
9 bits. The 9th bit is taken from the FIFO data (normal mode).
5 : 9_BITS_TBIT
9 bits. The 9th bit is set by the value of TBIT (fixed mode).
End of enumeration elements list.
TSCEN : Transmitter Smartcard Parity Response Enable.
bits : 28 - 28 (1 bit)
Enumeration:
0 : DISABLED
The transmitter does not check for a Smartcard parity error response.
1 : ENABLED
The transmitter checks for a Smartcard parity error response.
End of enumeration elements list.
TIRDAEN : Transmitter IrDA Enable.
bits : 29 - 29 (1 bit)
Enumeration:
0 : DISABLED
Disable IrDA transmit mode.
1 : ENABLED
Enable IrDA transmit mode.
End of enumeration elements list.
TINVEN : Transmitter Invert Enable.
bits : 30 - 30 (1 bit)
Enumeration:
0 : DISABLED
Do not invert the TX pin signals (the TX idle state is high).
1 : ENABLED
Invert the TX pin signals (the TX idle state is low).
End of enumeration elements list.
Module Mode Select
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCCKMD : RTC Clock Mode.
bits : 8 - 8 (1 bit)
Enumeration:
0 : APBCLK
UART clocked from the APB clock. The RBAUD and TBAUD controls will use the APB clock mode to determine the baudrate unless RTCBDMD = 1.
1 : RTC0TCLK
UART clocked from RTC0TCLK. The RBAUD and TBAUD controls will use the RTC0TCLK mode to determine the baudrate. Software should only set this bit to one when the UART is idle.
End of enumeration elements list.
RTCBDMD : RTC Baud Rate Mode.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
The RBAUD and TBAUD controls use the RTCCKMD setting to determine whether to use APB clock mode (RTCCKMD = 0) or the RTC0TCLK mode (RTCCKMD = 1). Use this setting when APB clock != RTC0TCLK.
1 : ENABLED
The RBAUD and TBAUD controls use RTC0TCLK mode. Use this setting when APB clock = RTC0TCLK and RTCCKMD = 0 to force the RBAUD and TBAUD controls into RTC0TCLK mode.
End of enumeration elements list.
FORCECLK : Force Clock On.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
UART clock is only on when necessary.
1 : ENABLED
Force the UART clock to always be on.
End of enumeration elements list.
CLKBUSY : Clock Switch Busy Status.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : IDLE
Clock switch completed.
1 : BUSY
Clock switch in progress.
End of enumeration elements list.
RXCLKSW : Receive Automatic Clock Switch.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
UART will always use the selected clock for receive operations.
1 : ENABLED
UART will automatically switch from RTC0TCLK to the APB clock when a receive interrupt is pending.
End of enumeration elements list.
TXCLKSW : Transmit Automatic Clock Switch.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
UART will always use the selected clock for transmit operations.
1 : ENABLED
UART will automatically switch from RTC0TCLK to the APB clock when a transmit interrupt is pending.
End of enumeration elements list.
DBGMD : UART Debug Mode.
bits : 16 - 16 (1 bit)
Enumeration:
0 : RUN
The UART module will continue to operate while the core is halted in debug mode.
1 : HALT
A debug breakpoint will cause the UART module to halt. Any active transmissions and receptions will complete first.
End of enumeration elements list.
LBMD : Loop Back Mode.
bits : 18 - 19 (2 bit)
Enumeration:
0 : DISABLED
Loop back is disabled and the TX and RX signals are connected to the corresponding external pins.
1 : RXONLY
Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device.
2 : TXONLY
Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX.
3 : BOTH
Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX.
End of enumeration elements list.
DUPLEXMD : Duplex Mode.
bits : 27 - 27 (1 bit)
Enumeration:
0 : FULL_DUPLEX
Full-duplex mode. The transmitter and receiver can operate simultaneously.
1 : HALF_DUPLEX
Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active.
End of enumeration elements list.
ITSEN : Idle TX Tristate Enable.
bits : 30 - 30 (1 bit)
Enumeration:
0 : DISABLED
The TX pin is always an output in this mode, even when idle.
1 : ENABLED
The TX pin is tristated when idle.
End of enumeration elements list.
Flow Control
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX : RX Pin Status.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : LOW
RX pin (after optional inversion) is low.
1 : HIGH
RX pin (after optional inversion) is high.
End of enumeration elements list.
TXOEN : TX Output Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
The pin assigned to TX is controlled by the direct port output value.
1 : ENABLED
The pin assigned to TX is controlled by the UART.
End of enumeration elements list.
TX : TX State.
bits : 17 - 17 (1 bit)
Enumeration:
0 : LOW
The TX pin (before optional inversion) is low.
1 : HIGH
The TX pin (before optional inversion) is high.
End of enumeration elements list.
TIRDAPW : Transmit IrDA Pulse Width.
bits : 28 - 29 (2 bit)
Enumeration:
0 : 1_16TH
The IrDA pulse width is 1/16th of a bit period.
1 : 1_8TH
The IrDA pulse width is 1/8th of a bit period.
2 : 3_16TH
The IrDA pulse width is 3/16th of a bit period.
3 : 1_4TH
The IrDA pulse width is 1/4th of a bit period.
End of enumeration elements list.
Module Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFRMERI : Receive Frame Error Interrupt Flag.
bits : 0 - 0 (1 bit)
Enumeration:
0 : NOT_SET
Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt.
1 : SET
Read: A frame error occurred. Write: Force a frame error interrupt.
End of enumeration elements list.
RPARERI : Receive Parity Error Interrupt Flag.
bits : 1 - 1 (1 bit)
Enumeration:
0 : NOT_SET
Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt.
1 : SET
Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt.
End of enumeration elements list.
ROREI : Receive Overrun Error Interrupt Flag.
bits : 2 - 2 (1 bit)
Enumeration:
0 : NOT_SET
Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt.
1 : SET
Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt.
End of enumeration elements list.
RDREQI : Receive Data Request Interrupt Flag.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
Fewer than RFTH FIFO entries are filled with data.
1 : SET
At least RFTH FIFO entries are filled with data.
End of enumeration elements list.
RERIEN : Receive Error Interrupt Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DISABLED
Disable the receive error interrupt.
1 : ENABLED
Enable the receive error interrupt. A receive interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1.
End of enumeration elements list.
RDREQIEN : Receive Data Request Interrupt Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the read data request interrupt.
1 : ENABLED
Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1.
End of enumeration elements list.
MATMD : Match Mode.
bits : 8 - 9 (2 bit)
Enumeration:
0 : OFF
Disable the match function.
1 : MCE
(MCE) Data whose last data bit equals RBIT is accepted and stored.
2 : FRAME
(Frame) A framing error is asserted if the last received data bit matches RBIT.
3 : STORE
(Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting.
End of enumeration elements list.
RABDEN : Receiver Auto-Baud Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Disable receiver auto-baud.
1 : ENABLED
Enable receiver auto-baud.
End of enumeration elements list.
RBUSYF : Receiver Busy Flag.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The UART receiver is idle.
1 : SET
The UART receiver is receiving data.
End of enumeration elements list.
RBIT : Last Receive Bit.
bits : 12 - 12 (1 bit)
Enumeration:
0 : NOT_SET
None
1 : SET
None
End of enumeration elements list.
ROSEN : Receiver One-Shot Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Disable one-shot receive mode.
1 : ENABLED
Enable one-shot receive mode.
End of enumeration elements list.
RINH : Receiver Inhibit.
bits : 14 - 14 (1 bit)
Enumeration:
0 : INACTIVE
The receiver operates normally.
1 : ACTIVE
The receiver will complete any ongoing reception, but ignore all traffic after that.
End of enumeration elements list.
REN : Receiver Enable.
bits : 15 - 15 (1 bit)
Enumeration:
0 : DISABLED
Disable the receiver. The receiver can receive one data transaction only if ROSEN is set.
1 : ENABLED
Enable the receiver.
End of enumeration elements list.
TSCERI : Smartcard Parity Error Interrupt Flag.
bits : 16 - 16 (1 bit)
Enumeration:
0 : NOT_SET
Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt.
1 : SET
Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt.
End of enumeration elements list.
TDREQI : Transmit Data Request Interrupt Flag.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The transmitter is not requesting more FIFO data.
1 : SET
The transmitter is requesting more FIFO data.
End of enumeration elements list.
TCPTI : Transmit Complete Interrupt Flag.
bits : 19 - 19 (1 bit)
Enumeration:
0 : NOT_SET
Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt.
1 : SET
Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt.
End of enumeration elements list.
TCPTTH : Transmit Complete Threshold.
bits : 20 - 20 (1 bit)
Enumeration:
0 : SET_ON_TX
The TCPTI flag is set after each data transmission.
1 : SET_ON_EMPTY
The TCPTI flag is set after transmission of the last available data.
End of enumeration elements list.
TERIEN : Transmit Error Interrupt Enable.
bits : 21 - 21 (1 bit)
Enumeration:
0 : DISABLED
Disable the transmit error interrupt.
1 : ENABLED
Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1.
End of enumeration elements list.
TDREQIEN : Transmit Data Request Interrupt Enable.
bits : 22 - 22 (1 bit)
Enumeration:
0 : DISABLED
Disable the transmit data request interrupt.
1 : ENABLED
Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1.
End of enumeration elements list.
TCPTIEN : Transmit Complete Interrupt Enable.
bits : 23 - 23 (1 bit)
Enumeration:
0 : DISABLED
Disable the transmit complete interrupt.
1 : ENABLED
Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1.
End of enumeration elements list.
TBUSYF : Transmitter Busy Flag.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The UART transmitter is idle.
1 : SET
The UART transmitter is active and transmitting.
End of enumeration elements list.
TBIT : Last Transmit Bit.
bits : 28 - 28 (1 bit)
Enumeration:
0 : NOT_SET
None
1 : SET
None
End of enumeration elements list.
TINH : Transmit Inhibit.
bits : 30 - 30 (1 bit)
Enumeration:
0 : INACTIVE
The transmitter operates normally.
1 : ACTIVE
Transmissions are inhibited. The transmitter will stall after any current transmission is complete.
End of enumeration elements list.
TEN : Transmitter Enable.
bits : 31 - 31 (1 bit)
Enumeration:
0 : DISABLED
Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO.
1 : ENABLED
Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO.
End of enumeration elements list.
Inter-Packet Delay
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPDELAY : Inter-Packet Delay.
bits : 16 - 23 (8 bit)
Transmit and Receive Baud Rate
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBAUD : Receiver Baud Rate Control.
bits : 0 - 15 (16 bit)
TBAUD : Transmitter Baud Rate Control.
bits : 16 - 31 (16 bit)
FIFO Control
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCNT : Receive FIFO Count.
bits : 0 - 2 (3 bit)
access : read-only
RFTH : Receive FIFO Threshold.
bits : 4 - 5 (2 bit)
Enumeration:
0 : ONE
A read data request interrupt (RDREQI) is asserted when >= 1 FIFO entry is full.
1 : TWO
A read data request interrupt (RDREQI) is asserted when >= 2 FIFO entries are full.
2 : THREE
A read data request interrupt (RDREQI) is asserted when >= 3 FIFO entries are full.
3 : FOUR
A read data request interrupt (RDREQI) is asserted when >= 4 FIFO entries are full.
End of enumeration elements list.
RFIFOFL : Receive FIFO Flush.
bits : 8 - 8 (1 bit)
Enumeration:
1 : SET
Flush the contents of the receive FIFO and any data in the receive shift register.
End of enumeration elements list.
RFERI : Receive FIFO Error Interrupt Flag.
bits : 9 - 9 (1 bit)
Enumeration:
0 : NOT_SET
A receive FIFO error has not occurred since RFERI was last cleared.
1 : SET
A receive FIFO error occurred.
End of enumeration elements list.
RSRFULLF : Receive Shift Register Full Flag.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The receive data shift register is not full.
1 : SET
The receive data shift register is full.
End of enumeration elements list.
TCNT : Transmit FIFO Count.
bits : 16 - 18 (3 bit)
access : read-only
TFTH : Transmit FIFO Threshold.
bits : 20 - 21 (2 bit)
Enumeration:
0 : ONE
A transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO entry is empty.
1 : TWO
A transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO entries are empty.
2 : THREE
A transmit data request interrupt (TDREQI) is asserted when >= 3 FIFO entries are empty.
3 : FOUR
A transmit data request interrupt (TDREQI) is asserted when >= 4 FIFO entries are empty.
End of enumeration elements list.
TFIFOFL : Transmit FIFO Flush.
bits : 24 - 24 (1 bit)
Enumeration:
1 : SET
Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed.
End of enumeration elements list.
TFERI : Transmit FIFO Error Interrupt Flag.
bits : 25 - 25 (1 bit)
Enumeration:
0 : NOT_SET
A transmit FIFO error has not occurred since TFERI was last cleared.
1 : SET
A transmit FIFO error occurred.
End of enumeration elements list.
TSRFULLF : Transmit Shift Register Full Flag.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The transmit shift register is not full.
1 : SET
The transmit shift register is full.
End of enumeration elements list.
FIFO Input/Output Data
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : FIFO Data.
bits : 0 - 31 (32 bit)
Clock Divider
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : Clock Divider.
bits : 0 - 1 (2 bit)
Enumeration:
0 : DIV1
Divide by 1.
1 : DIV2
Divide by 2.
2 : DIV4
Divide by 4.
End of enumeration elements list.
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