\n

LCD_0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONFIG

CLKCONTROL

BLKCONTROL

SEGCONTROL

CTRSTCONTROL

VBMCONTROL

SEGMASK0

SEGMASK1

SEGDATA0

SEGDATA1

SEGDATA2

SEGDATA3

SEGDATA4


CONFIG

Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCDEN CPFPDEN MCDEN RTCCEN BIASEN DCDCBIASEN DCDCSTDBYEN CPBEN HCVLPMEN VBMLPEN CPOLPEN CMPBLPEN BIASSEN RBGSEN CPACEN FBIASCEN HCVCBYPEN HCVCFOEN HCVCHMD HCVCBMD CPCS

LCDEN : Module Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : DISABLED

Disable the LCD module.

1 : ENABLED

Enable the LCD module.

End of enumeration elements list.

CPFPDEN : Charge Pump Full Power Drive Mode Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : DISABLED

Disable the LCD charge pump's full power drive mode. The charge pump draws less power but operates with reduced output current capabilities.

1 : ENABLED

Enable the LCD charge pump's full output drive mode. The charge pump operates at full power.

End of enumeration elements list.

MCDEN : LCD Missing Clock Detector Enable.
bits : 3 - 3 (1 bit)

Enumeration:

0 : DISABLED

Disable the dedicated LCD missing clock detector.

1 : ENABLED

Enable the dedicated LCD missing clock detector.

End of enumeration elements list.

RTCCEN : RTC Clock Request Enable.
bits : 4 - 4 (1 bit)

Enumeration:

0 : DISABLED

The LCD module does not require the RTC clock.

1 : ENABLED

The LCD module requires an active and valid RTC clock (RTC0TCLK).

End of enumeration elements list.

BIASEN : Bias Enable.
bits : 5 - 5 (1 bit)

Enumeration:

0 : DISABLED

Disable the LCD bias current.

1 : ENABLED

Enable the LCD bias current.

End of enumeration elements list.

DCDCBIASEN : DCDC Bias Output Enable.
bits : 6 - 6 (1 bit)

Enumeration:

0 : DISABLED

Disable the secondary bias current output.

1 : ENABLED

Enable the secondary bias current output.

End of enumeration elements list.

DCDCSTDBYEN : DCDC Bias Standby Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : DISABLED

The DCDC bias is enabled in Power Mode 8.

1 : ENABLED

The DCDC bias is disabled in Power Mode 8.

End of enumeration elements list.

CPBEN : Charge Pump Bypass Enable.
bits : 8 - 8 (1 bit)

Enumeration:

0 : DISABLED

The LCD charge pump generates the VLCD voltage.

1 : ENABLED

Bypass the LCD charge pump and connect VLCD directly to VBAT.

End of enumeration elements list.

HCVLPMEN : High-Contrast-Voltage Low-Power Mode Enable.
bits : 9 - 9 (1 bit)

Enumeration:

0 : DISABLED

Disable the high-contrast-voltage low-power mode.

1 : ENABLED

Enable the high-contrast-voltage low-power mode. This mode reduces power consumption when VLCD is higher than VBAT.

End of enumeration elements list.

VBMLPEN : VBAT Monitor Low Power Enable.
bits : 10 - 10 (1 bit)

Enumeration:

0 : DISABLED

Disable the LCD VBAT Monitor low power mode.

1 : ENABLED

Enable the LCD VBAT Monitor low power mode.

End of enumeration elements list.

CPOLPEN : Charge-Pump Oscillator Low-Power Enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : DISABLED

Disable the charge-pump oscillator low-power mode.

1 : ENABLED

Enable the charge-pump oscillator low-power mode.

End of enumeration elements list.

CMPBLPEN : Comparator Buffer Low-Power Enable.
bits : 12 - 12 (1 bit)

Enumeration:

0 : DISABLED

Disable the comparator buffer low-power mode.

1 : ENABLED

Enable the comparator buffer low-power mode.

End of enumeration elements list.

BIASSEN : Bias Switching Enable.
bits : 13 - 13 (1 bit)

Enumeration:

0 : DISABLED

Disable bias switching.

1 : ENABLED

Enable bias switching.

End of enumeration elements list.

RBGSEN : Reference Band Gap Switching Enable.
bits : 14 - 14 (1 bit)

Enumeration:

0 : DISABLED

Disable reference band gap switching mode.

1 : ENABLED

Enable reference band gap switching mode.

End of enumeration elements list.

CPACEN : Charge-Pump Auto-Contrast Enable.
bits : 16 - 16 (1 bit)

Enumeration:

0 : DISABLED

VLCD continues to track VBAT when VBAT drops below the programmed VLCD value.

1 : ENABLED

The module automatically enables the charge pump and maintains the VLCD voltage when VBAT drops below the programmed VBAT monitor level.

End of enumeration elements list.

FBIASCEN : Force Bias Continuous Mode Enable.
bits : 17 - 17 (1 bit)

Enumeration:

0 : DISABLED

The bias operates as configured.

1 : ENABLED

Force the bias to operate in continuous mode. The bias will cleanly transition from its configuration settings to continuous mode.

End of enumeration elements list.

HCVCBYPEN : High-Contrast-Voltage Comparator Bypass Enable.
bits : 24 - 24 (1 bit)

Enumeration:

0 : DISABLED

Hardware enables the high-contrast-voltage comparator as needed.

1 : ENABLED

High-contrast-voltage comparator in bypass mode.

End of enumeration elements list.

HCVCFOEN : High-Contrast-Voltage Comparator Force On Enable.
bits : 25 - 25 (1 bit)

Enumeration:

0 : DISABLED

Hardware enables the high-contrast-voltage comparator as needed.

1 : ENABLED

High-contrast-voltage comparator force on enabled.

End of enumeration elements list.

HCVCHMD : High-Contrast-Voltage Comparator Hysteresis.
bits : 26 - 26 (1 bit)

Enumeration:

0 : HIGH

Set the high-contrast-voltage comparator to high-hysteresis mode. This is the recommended setting.

1 : LOW

Set the high-contrast-voltage comparator to low-hysteresis mode.

End of enumeration elements list.

HCVCBMD : High-Contrast-Voltage Comparator Bias.
bits : 27 - 27 (1 bit)

Enumeration:

0 : HIGH

Set the high-contrast-voltage comparator to high bias mode.

1 : LOW

Set the high-contrast-voltage comparator to low-bias mode. This is the recommended setting.

End of enumeration elements list.

CPCS : High-Contrast-Voltage Comparator Status.
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : VBAT

VBAT is greater than VLCD.

1 : VLCD

VLCD is greater than VBAT.

End of enumeration elements list.


CLKCONTROL

Clock Control
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCONTROL CLKCONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV RTCCLKDIV

CLKDIV : Clock Divider.
bits : 0 - 9 (10 bit)

RTCCLKDIV : RTC Input Clock Divider.
bits : 28 - 29 (2 bit)

Enumeration:

0 : DIVIDE_BY_1

None

1 : DIVIDE_BY_2

None

2 : DIVIDE_BY_4

None

3 : DIVIDE_BY_8

None

End of enumeration elements list.


BLKCONTROL

Blinking Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLKCONTROL BLKCONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLKMASK BLKREXP

BLKMASK : Hardware Blinking Enable.
bits : 0 - 7 (8 bit)

BLKREXP : Hardware Blinking Rate Divider Exponent.
bits : 8 - 11 (4 bit)

Enumeration:

2 : DIVIDE_BY_2

Set blink rate divider to divide by 2.

3 : DIVIDE_BY_4

Set blink rate divider to divide by 4.

4 : DIVIDE_BY_8

Set blink rate divider to divide by 8.

5 : DIVIDE_BY_16

Set blink rate divider to divide by 16.

6 : DIVIDE_BY_32

Set blink rate divider to divide by 32.

7 : DIVIDE_BY_64

Set blink rate divider to divide by 64.

8 : DIVIDE_BY_128

Set blink rate divider to divide by 128.

9 : DIVIDE_BY_256

Set blink rate divider to divide by 256.

10 : DIVIDE_BY_512

Set blink rate divider to divide by 512.

11 : DIVIDE_BY_1024

Set blink rate divider to divide by 1024.

12 : DIVIDE_BY_2048

Set blink rate divider to divide by 2048.

13 : DIVIDE_BY_4096

Set blink rate divider to divide by 4096.

End of enumeration elements list.


SEGCONTROL

Segment Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGCONTROL SEGCONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIASMD SEGMD BLANKEN RPHEN RPHMD

BIASMD : Hardware Bias Mode.
bits : 0 - 0 (1 bit)

Enumeration:

0 : ONE_THIRD

Select 1/3 bias. Use for three-mux segment mode and four-mux segment mode.

1 : ONE_HALF

Select 1/2 bias. Use for two-mux segment mode.

End of enumeration elements list.

SEGMD : Segment Mode.
bits : 1 - 2 (2 bit)

Enumeration:

0 : STATIC

Select static segment mode with one common COMn.0 used.

1 : 2_MUX

Select two-mux segment mode with two commons (COMn.0 and COMn.1) used.

2 : 3_MUX

Select three-mux segment mode with three commons (COMn.0, COMn.1, COMn.2) used.

3 : 4_MUX

Select four-mux segment mode with four commons (COMn.0, COMn.1, COMn.2 and COMn.3) used.

End of enumeration elements list.

BLANKEN : Segment Blank Enable.
bits : 4 - 4 (1 bit)

Enumeration:

0 : DISABLED

Operate segments normally.

1 : ENABLED

Blank the LCD by disabling all LCD segment and common pins.

End of enumeration elements list.

RPHEN : Reset Phase Enable.
bits : 5 - 5 (1 bit)

Enumeration:

0 : DISABLED

Hardware switches the LCD segment and common pin controls directly from one state to another.

1 : ENABLED

Hardware switches the LCD segment and common pin controls to intermediate states for several RTC clock cycles before switching to the next state.

End of enumeration elements list.

RPHMD : Reset Phase Mode.
bits : 6 - 8 (3 bit)


CTRSTCONTROL

Contrast Control
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRSTCONTROL CTRSTCONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRST CTRSTBF CPCDEN

CTRST : Contrast Voltage.
bits : 0 - 4 (5 bit)

CTRSTBF : Contrast Busy Flag.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

An update of the internal contrast registers is not in progress.

1 : SET

The internal contrast registers are busy updating.

End of enumeration elements list.

CPCDEN : Charge Pump Capacitor Divider Enable.
bits : 29 - 29 (1 bit)

Enumeration:

0 : DISABLED

Disable the charge pump capacitor divider.

1 : ENABLED

Enable the charge pump capacitor divider.

End of enumeration elements list.


VBMCONTROL

VBAT Monitor Control
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBMCONTROL VBMCONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBMTH VBMBF VBMCLKDIV VBMCDEN VBMOEN VBMEN

VBMTH : VBAT Monitor Threshold.
bits : 0 - 4 (5 bit)

VBMBF : VBAT Monitor Busy Flag.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

An update of the internal VBAT monitor registers is not in progress.

1 : SET

The internal VBAT monitor registers are busy updating.

End of enumeration elements list.

VBMCLKDIV : VBAT Monitor Clock Divider.
bits : 22 - 24 (3 bit)

VBMCDEN : VBAT Monitor Capacitor Divider Enable.
bits : 29 - 29 (1 bit)

Enumeration:

0 : DISABLED

Disable the VBAT monitor capacitor divider.

1 : ENABLED

Enable the VBAT monitor capacitor divider.

End of enumeration elements list.

VBMOEN : VBAT Monitor Offset Enable.
bits : 30 - 30 (1 bit)

Enumeration:

0 : DISABLED

The VBAT monitor threshold set by the VBMTH field functions as an absolute threshold value for the VBAT monitor.

1 : ENABLED

The VBAT monitor threshold set by the VBMTH field functions as an offset to the LCD contrast value set by CTRSTMD.

End of enumeration elements list.

VBMEN : VBAT Monitor Enable.
bits : 31 - 31 (1 bit)

Enumeration:

0 : DISABLED

Disable the VBAT monitor.

1 : ENABLED

Enable the VBAT monitor.

End of enumeration elements list.


SEGMASK0

Segment Mask 0
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGMASK0 SEGMASK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGEN

SEGEN : Segment Enable.
bits : 0 - 31 (32 bit)


SEGMASK1

Segment Mask 1
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGMASK1 SEGMASK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGEN

SEGEN : Segment Enable.
bits : 0 - 7 (8 bit)


SEGDATA0

Segment Data 0
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGDATA0 SEGDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGPIN0 SEGPIN1 SEGPIN2 SEGPIN3 SEGPIN4 SEGPIN5 SEGPIN6 SEGPIN7

SEGPIN0 : Segment LCDn.0 Control.
bits : 0 - 3 (4 bit)

SEGPIN1 : Segment LCDn.1 Control.
bits : 4 - 7 (4 bit)

SEGPIN2 : Segment LCDn.2 Control.
bits : 8 - 11 (4 bit)

SEGPIN3 : Segment LCDn.3 Control.
bits : 12 - 15 (4 bit)

SEGPIN4 : Segment LCDn.4 Control.
bits : 16 - 19 (4 bit)

SEGPIN5 : Segment LCDn.5 Control.
bits : 20 - 23 (4 bit)

SEGPIN6 : Segment LCDn.6 Control.
bits : 24 - 27 (4 bit)

SEGPIN7 : Segment LCDn.7 Control.
bits : 28 - 31 (4 bit)


SEGDATA1

Segment Data 1
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGDATA1 SEGDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGPIN8 SEGPIN9 SEGPIN10 SEGPIN11 SEGPIN12 SEGPIN13 SEGPIN14 SEGPIN15

SEGPIN8 : Segment LCDn.8 Control.
bits : 0 - 3 (4 bit)

SEGPIN9 : Segment LCDn.9 Control.
bits : 4 - 7 (4 bit)

SEGPIN10 : Segment LCDn.10 Control.
bits : 8 - 11 (4 bit)

SEGPIN11 : Segment LCDn.11 Control.
bits : 12 - 15 (4 bit)

SEGPIN12 : Segment LCDn.12 Control.
bits : 16 - 19 (4 bit)

SEGPIN13 : Segment LCDn.13 Control.
bits : 20 - 23 (4 bit)

SEGPIN14 : Segment LCDn.14 Control.
bits : 24 - 27 (4 bit)

SEGPIN15 : Segment LCDn.15 Control.
bits : 28 - 31 (4 bit)


SEGDATA2

Segment Data 2
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGDATA2 SEGDATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGPIN16 SEGPIN17 SEGPIN18 SEGPIN19 SEGPIN20 SEGPIN21 SEGPIN22 SEGPIN23

SEGPIN16 : Segment LCDn.16 Control.
bits : 0 - 3 (4 bit)

SEGPIN17 : Segment LCDn.17 Control.
bits : 4 - 7 (4 bit)

SEGPIN18 : Segment LCDn.18 Control.
bits : 8 - 11 (4 bit)

SEGPIN19 : Segment LCDn.19 Control.
bits : 12 - 15 (4 bit)

SEGPIN20 : Segment LCDn.20 Control.
bits : 16 - 19 (4 bit)

SEGPIN21 : Segment LCDn.21 Control.
bits : 20 - 23 (4 bit)

SEGPIN22 : Segment LCDn.22 Control.
bits : 24 - 27 (4 bit)

SEGPIN23 : Segment LCDn.23 Control.
bits : 28 - 31 (4 bit)


SEGDATA3

Segment Data 3
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGDATA3 SEGDATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGPIN24 SEGPIN25 SEGPIN26 SEGPIN27 SEGPIN28 SEGPIN29 SEGPIN30 SEGPIN31

SEGPIN24 : Segment LCDn.24 Control.
bits : 0 - 3 (4 bit)

SEGPIN25 : Segment LCDn.25 Control.
bits : 4 - 7 (4 bit)

SEGPIN26 : Segment LCDn.26 Control.
bits : 8 - 11 (4 bit)

SEGPIN27 : Segment LCDn.27 Control.
bits : 12 - 15 (4 bit)

SEGPIN28 : Segment LCDn.28 Control.
bits : 16 - 19 (4 bit)

SEGPIN29 : Segment LCDn.29 Control.
bits : 20 - 23 (4 bit)

SEGPIN30 : Segment LCDn.30 Control.
bits : 24 - 27 (4 bit)

SEGPIN31 : Segment LCDn.31 Control.
bits : 28 - 31 (4 bit)


SEGDATA4

Segment Data 4
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGDATA4 SEGDATA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGPIN32 SEGPIN33 SEGPIN34 SEGPIN35 SEGPIN36 SEGPIN37 SEGPIN38 SEGPIN39

SEGPIN32 : Segment LCDn.32 Control.
bits : 0 - 3 (4 bit)

SEGPIN33 : Segment LCDn.33 Control.
bits : 4 - 7 (4 bit)

SEGPIN34 : Segment LCDn.34 Control.
bits : 8 - 11 (4 bit)

SEGPIN35 : Segment LCDn.35 Control.
bits : 12 - 15 (4 bit)

SEGPIN36 : Segment LCDn.36 Control.
bits : 16 - 19 (4 bit)

SEGPIN37 : Segment LCDn.37 Control.
bits : 20 - 23 (4 bit)

SEGPIN38 : Segment LCDn.38 Control.
bits : 24 - 27 (4 bit)

SEGPIN39 : Segment LCDn.39 Control.
bits : 28 - 31 (4 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.