Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Global Port Control 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT0SEL : External Interrupt 0 Pin Selection.
bits : 0 - 3 (4 bit)
Enumeration:
0 : INT0_0
Select INT0.0
1 : INT0_1
Select INT0.1
2 : INT0_2
Select INT0.2
3 : INT0_3
Select INT0.3
4 : INT0_4
Select INT0.4
5 : INT0_5
Select INT0.5
6 : INT0_6
Select INT0.6
7 : INT0_7
Select INT0.7
8 : INT0_8
Select INT0.8
9 : INT0_9
Select INT0.9
10 : INT0_10
Select INT0.10
11 : INT0_11
Select INT0.11
12 : INT0_12
Select INT0.12
13 : INT0_13
Select INT0.13
14 : INT0_14
Select INT0.14
15 : INT0_15
Select INT0.15
End of enumeration elements list.
INT0POL : External Interrupt 0 Polarity.
bits : 4 - 4 (1 bit)
Enumeration:
0 : LOW
A low value or falling edge on the selected pin will cause interrupt.
1 : HIGH
A high value or rising edge on the selected pin will cause interrupt.
End of enumeration elements list.
INT0MD : External Interrupt 0 Mode.
bits : 5 - 6 (2 bit)
Enumeration:
0 : LEVEL
Interrupt on logic level at pin, as selected by the INT0POL field.
1 : EDGE
Interrupt on either rising or falling edge, as selected by the INT0POL field.
2 : DUAL_EDGE
Interrupt on both rising and falling edges (ignores INT0POL).
End of enumeration elements list.
INT0EN : External Interrupt 0 Enable.
bits : 7 - 7 (1 bit)
Enumeration:
0 : DISABLED
Disable external interrupt 0.
1 : ENABLED
Enable external interrupt 0.
End of enumeration elements list.
INT1SEL : External Interrupt 1 Pin Selection.
bits : 8 - 11 (4 bit)
Enumeration:
0 : INT1_0
Select INT1.0
1 : INT1_1
Select INT1.1
2 : INT1_2
Select INT1.2
3 : INT1_3
Select INT1.3
4 : INT1_4
Select INT1.4
5 : INT1_5
Select INT1.5
6 : INT1_6
Select INT1.6
7 : INT1_7
Select INT1.7
8 : INT1_8
Select INT1.8
9 : INT1_9
Select INT1.9
10 : INT1_10
Select INT1.10
11 : INT1_11
Select INT1.11
12 : INT1_12
Select INT1.12
13 : INT1_13
Select INT1.13
14 : INT1_14
Select INT1.14
15 : INT1_15
Select INT1.15
End of enumeration elements list.
INT1POL : External Interrupt 1 Polarity.
bits : 12 - 12 (1 bit)
Enumeration:
0 : LOW
A low value or falling edge on the selected pin will cause interrupt.
1 : HIGH
A high value or rising edge on the selected pin will cause interrupt.
End of enumeration elements list.
INT1MD : External Interrupt 1 Mode.
bits : 13 - 14 (2 bit)
Enumeration:
0 : LEVEL
Interrupt on logic level at pin, as selected by the INT1POL field.
1 : EDGE
Interrupt on either rising or falling edge, as selected by the INT1POL field.
2 : DUAL_EDGE
Interrupt on both rising and falling edges (ignores INT1POL).
End of enumeration elements list.
INT1EN : External Interrupt 1 Enable.
bits : 15 - 15 (1 bit)
Enumeration:
0 : DISABLED
Disable external interrupt 1.
1 : ENABLED
Enable external interrupt 1.
End of enumeration elements list.
PGTIMER : Pulse Generator Timer.
bits : 24 - 28 (5 bit)
PGDONEF : Pulse Generator Timer Done Flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
Firmware has written to the PBPGPHASE register, but the Pulse Generator timer has not expired.
1 : SET
The Pulse Generator cycle finished since the last time PBPGPHASE was written.
End of enumeration elements list.
Global Port Control 1
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JTAGEN : JTAG Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
JTAG functionality is not pinned out.
1 : ENABLED
JTAG functionality is pinned out.
End of enumeration elements list.
ETMEN : ETM Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
ETM not pinned out.
1 : ENABLED
ETM is enabled and pinned out.
End of enumeration elements list.
SWVEN : SWV Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
SWV is not pinned out.
1 : ENABLED
SWV is enabled and pinned out.
End of enumeration elements list.
SPI1SEL : SPI1 Fixed Port Selection.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disconnect SPI1 from the dedicated pins.
1 : ENABLED
Connect SPI1 to the dedicated pins.
End of enumeration elements list.
PMATCHEN : Port Match Interrupt Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Disable the port match logic. The PBnMAT registers are not read/write accessible on the APB bus.
1 : ENABLED
Enable the port match logic to generate a port match interrupt. The PBnMAT registers are read/write accessible on the APB bus.
End of enumeration elements list.
LPTOSEL : Low Power Timer Output Pin Select.
bits : 12 - 12 (1 bit)
Enumeration:
0 : LPT0OUT0
Route the Low Power Timer output to LPT0OUT0.
1 : LPT0OUT1
Route the Low Power Timer output to LPT0OUT1.
End of enumeration elements list.
LOCK : Port Bank Configuration Lock.
bits : 31 - 31 (1 bit)
Enumeration:
0 : UNLOCKED
Port Bank Configuration and Control registers are unlocked.
1 : LOCKED
The following registers are locked from write access: CONTROL1, XBAR0, and all PBSKIP registers.
End of enumeration elements list.
Crossbar 0 Control
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USART0EN : USART0 Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable USART0 RX and TX on Crossbar 0.
1 : ENABLED
Enable USART0 RX and TX on Crossbar 0.
End of enumeration elements list.
USART0FCEN : USART0 Flow Control Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable USART0 flow control on Crossbar 0.
1 : ENABLED
Enable USART0 flow control on Crossbar 0.
End of enumeration elements list.
USART0CEN : USART0 Clock Signal Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable USART0 clock on Crossbar 0.
1 : ENABLED
Enable USART0 clock on Crossbar 0.
End of enumeration elements list.
DMA0T0EN : DMA Trigger 0 Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
Disable the DMA trigger 0 on Crossbar 0.
1 : ENABLED
Enable the DMA trigger 0 on Crossbar 0.
End of enumeration elements list.
DMA0T1EN : DMA Trigger 1 Enabled.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
Disable the DMA trigger 1 on Crossbar 0.
1 : ENABLED
Enable the DMA trigger 1 on Crossbar 0.
End of enumeration elements list.
IDAC0TEN : IDAC0 Trigger Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DISABLED
Disable the IDAC0 trigger on Crossbar 0.
1 : ENABLED
Enable the IDAC0 trigger on Crossbar 0.
End of enumeration elements list.
SPI0EN : SPI0 Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable SPI0 SCK, MISO, and MOSI on Crossbar 0.
1 : ENABLED
Enable SPI0 SCK, MISO, and MOSI on Crossbar 0.
End of enumeration elements list.
SPI0NSSEN : SPI0 NSS Pin Enable.
bits : 7 - 7 (1 bit)
Enumeration:
0 : DISABLED
Disable SPI0 NSS on Crossbar 0.
1 : ENABLED
Enable SPI0 NSS on Crossbar 0.
End of enumeration elements list.
EPCA0EN : EPCA0 Channel Enable.
bits : 8 - 10 (3 bit)
Enumeration:
0 : NONE
Disable all EPCA0 channels on Crossbar 0.
1 : CEX0_0
Enable EPCA0 CEX0 on Crossbar 0.
2 : CEX0_1
Enable EPCA0 CEX0 and CEX1 on Crossbar 0.
3 : CEX0_2
Enable EPCA0 CEX0, CEX1, and CEX2 on Crossbar 0.
4 : CEX0_3
Enable EPCA0 CEX0, CEX1, CEX2, and CEX3 on Crossbar 0.
5 : CEX0_4
Enable EPCA0 CEX0, CEX1, CEX2, CEX3, and CEX4 on Crossbar 0.
6 : CEX0_5
Enable EPCA0 CEX0, CEX1, CEX2, CEX3, CEX4, and CEX5 on Crossbar 0.
End of enumeration elements list.
EECI0EN : EPCA0 ECI Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Disable EPCA0 ECI on Crossbar 0.
1 : ENABLED
Enable EPCA0 ECI on Crossbar 0.
End of enumeration elements list.
I2C0EN : I2C0 Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Disable I2C0 SDA and SCL on Crossbar 0.
1 : ENABLED
Enable I2C0 SDA and SCL on Crossbar 0.
End of enumeration elements list.
CMP0SEN : Comparator 0 Synchronous Output (CMP0S) Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.
1 : ENABLED
Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.
End of enumeration elements list.
CMP0AEN : Comparator 0 Asynchronous Output (CMP0A) Enable.
bits : 14 - 14 (1 bit)
Enumeration:
0 : DISABLED
Disable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.
1 : ENABLED
Enable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.
End of enumeration elements list.
CMP1SEN : Comparator 1 Synchronous Output (CMP1S) Enable.
bits : 15 - 15 (1 bit)
Enumeration:
0 : DISABLED
Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.
1 : ENABLED
Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.
End of enumeration elements list.
CMP1AEN : Comparator 1 Asynchronous Output (CMP1A) Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
Disable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.
1 : ENABLED
Enable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.
End of enumeration elements list.
TMR0CTEN : TIMER0 T0CT Enable.
bits : 17 - 17 (1 bit)
Enumeration:
0 : DISABLED
Disable TIMER0 CT on Crossbar 0.
1 : ENABLED
Enable TIMER0 CT on Crossbar 0.
End of enumeration elements list.
TMR0EXEN : TIMER0 T0EX Enable.
bits : 18 - 18 (1 bit)
Enumeration:
0 : DISABLED
Disable TIMER0 EX on Crossbar 0.
1 : ENABLED
Enable TIMER0 EX on Crossbar 0.
End of enumeration elements list.
TMR1CTEN : TIMER1 T1CT Enable.
bits : 19 - 19 (1 bit)
Enumeration:
0 : DISABLED
Disable TIMER1 CT on Crossbar 0.
1 : ENABLED
Enable TIMER1 CT on Crossbar 0.
End of enumeration elements list.
TMR1EXEN : TIMER1 T1EX Enable.
bits : 20 - 20 (1 bit)
Enumeration:
0 : DISABLED
Disable TIMER1 EX on Crossbar 0.
1 : ENABLED
Enable TIMER1 EX on Crossbar 0.
End of enumeration elements list.
SARADC0TEN : SARADC0 Trigger Enable.
bits : 21 - 21 (1 bit)
Enumeration:
0 : DISABLED
Disable SARADC0 conversion start trigger on Crossbar 0.
1 : ENABLED
Enable SARADC0 conversion start trigger on Crossbar 0.
End of enumeration elements list.
AHBEN : AHB Clock Output Enable.
bits : 22 - 22 (1 bit)
Enumeration:
0 : DISABLED
Disable the AHB Clock / 16 output on Crossbar 0.
1 : ENABLED
Enable the AHB Clock / 16 output on Crossbar 0.
End of enumeration elements list.
XBAR0EN : Crossbar 0 Enable.
bits : 31 - 31 (1 bit)
Enumeration:
0 : DISABLED
Disable Crossbar 0.
1 : ENABLED
Enable Crossbar 0.
End of enumeration elements list.
Global Port Key
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Port Bank Key.
bits : 0 - 7 (8 bit)
Enumeration:
0 : LOCKED
Port Bank registers are locked and no valid values have been written to PBKEY.
1 : INTERMEDIATE
Port Bank registers are locked and the first valid value (0xA5) has been written to PBKEY.
2 : UNLOCKED
Port Bank registers are unlocked. Any subsequent writes to the Port Bank registers or PBKEY will lock the interface.
End of enumeration elements list.
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