\n
address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDEN : Module Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the LCD module.
1 : ENABLED
Enable the LCD module.
End of enumeration elements list.
CPFPDEN : Charge Pump Full Power Drive Mode Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable the LCD charge pump's full power drive mode. The charge pump draws less power but operates with reduced output current capabilities.
1 : ENABLED
Enable the LCD charge pump's full output drive mode. The charge pump operates at full power.
End of enumeration elements list.
MCDEN : LCD Missing Clock Detector Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
Disable the dedicated LCD missing clock detector.
1 : ENABLED
Enable the dedicated LCD missing clock detector.
End of enumeration elements list.
RTCCEN : RTC Clock Request Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
The LCD module does not require the RTC clock.
1 : ENABLED
The LCD module requires an active and valid RTC clock (RTC0TCLK).
End of enumeration elements list.
BIASEN : Bias Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DISABLED
Disable the LCD bias current.
1 : ENABLED
Enable the LCD bias current.
End of enumeration elements list.
DCDCBIASEN : DCDC Bias Output Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the secondary bias current output.
1 : ENABLED
Enable the secondary bias current output.
End of enumeration elements list.
DCDCSTDBYEN : DCDC Bias Standy Enable.
bits : 7 - 7 (1 bit)
Enumeration:
0 : DISABLED
The DCDC bias is enabled in Power Mode 8.
1 : ENABLED
The DCDC bias is disabled in Power Mode 8.
End of enumeration elements list.
CPBEN : Charge Pump Bypass Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
The LCD charge pump generates the VLCD voltage.
1 : ENABLED
Bypass the LCD charge pump and connect VLCD directly to VBAT.
End of enumeration elements list.
HCVLPMEN : High Contrast Voltage Low-Power Mode Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Disable the high contrast voltage low-power mode.
1 : ENABLED
Enable the high contrast voltage low-power mode. This mode reduces power consumption whenVLCD is higher than VBAT.
End of enumeration elements list.
VBMLPEN : VBAT Monitor Low Power Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Disable the LCD VBAT Monitor low power mode.
1 : ENABLED
Enable the LCD VBAT Monitor low power mode.
End of enumeration elements list.
CPOLPEN : Charge Pump Oscillator Low Power Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Disable the charge pump oscillator low power mode.
1 : ENABLED
Enable the charge pump oscillator low power mode.
End of enumeration elements list.
CMPBLPEN : Comparator Buffer Low Power Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Disable the comparator buffer low power mode.
1 : ENABLED
Enable the comparator buffer low power mode.
End of enumeration elements list.
BIASSEN : Bias Switching Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Disable bias switching.
1 : ENABLED
Enable bias switching.
End of enumeration elements list.
RBGSEN : Reference Bandgap Switching Enable.
bits : 14 - 14 (1 bit)
Enumeration:
0 : DISABLED
Disable reference bandgap switching mode.
1 : ENABLED
Disable reference bandgap switching mode.
End of enumeration elements list.
CPACEN : Charge Pump Auto-Contrast Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
VLCD continues to track VBAT when VBAT drops below the programmed VLCD value.
1 : ENABLED
The module automatically enables the charge pump and maintains the VLCD voltage when VBAT drops below the programmed VBAT monitor level.
End of enumeration elements list.
FBIASCEN : Force Bias Continuous Mode Enable.
bits : 17 - 17 (1 bit)
Enumeration:
0 : DISABLED
The bias operates as configured.
1 : ENABLED
Force the bias to operate in continuous mode. The bias will cleanly transition from its configuration settings to continuous mode.
End of enumeration elements list.
BIASBGR : Bias to Bandgap Switching Cycle Ratio.
bits : 18 - 21 (4 bit)
HCVCBYPEN : High Contrast Voltage Comparator Bypass Enable.
bits : 24 - 24 (1 bit)
Enumeration:
0 : DISABLED
Hardware enables the high contrast voltage comparator as needed.
1 : ENABLED
High contrast voltage comparator in bypass mode.
End of enumeration elements list.
HCVCFOEN : High Contrast Voltage Comparator Force On Enable.
bits : 25 - 25 (1 bit)
Enumeration:
0 : DISABLED
Hardware enables the high contrast voltage comparator as needed.
1 : ENABLED
High contrast voltage comparator force on enabled.
End of enumeration elements list.
HCVCHMD : High Contrast Voltage Comparator Hysteresis.
bits : 26 - 26 (1 bit)
Enumeration:
0 : LOW
Set the high contrast voltage comparator to low hysteresis mode.
1 : HIGH
Set the high contrast voltage comparator to high hysteresis mode.
End of enumeration elements list.
HCVCBMD : High Contrast Voltage Comparator Bias.
bits : 27 - 27 (1 bit)
Enumeration:
0 : LOW
Set the high contrast voltage comparator to low bias mode.
1 : HIGH
Set the high contrast voltage comparator to high bias mode.
End of enumeration elements list.
CPSMD : Charge Pump Supply Mode.
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : EXTERNAL
Select the external supply for the charge pump.
1 : VLCD
Select VLCD as the supply for the charge pump.
End of enumeration elements list.
Clock Control
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : Clock Divider.
bits : 0 - 9 (10 bit)
RTCCLKDIV : RTC Input Clock Divider.
bits : 28 - 29 (2 bit)
Enumeration:
0 : DIVIDE_BY_1
None
1 : DIVIDE_BY_2
None
2 : DIVIDE_BY_4
None
3 : DIVIDE_BY_8
None
End of enumeration elements list.
Blinking Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKMASK : Hardware Blinking Enable.
bits : 0 - 7 (8 bit)
BLKREXP : Hardware Blinking Rate Divider Exponent.
bits : 8 - 11 (4 bit)
Enumeration:
2 : DIVIDE_BY_2
Set blink rate divider to divide by 2.
3 : DIVIDE_BY_4
Set blink rate divider to divide by 4.
4 : DIVIDE_BY_8
Set blink rate divider to divide by 8.
5 : DIVIDE_BY_16
Set blink rate divider to divide by 16.
6 : DIVIDE_BY_32
Set blink rate divider to divide by 32.
7 : DIVIDE_BY_64
Set blink rate divider to divide by 64.
8 : DIVIDE_BY_128
Set blink rate divider to divide by 128.
9 : DIVIDE_BY_256
Set blink rate divider to divide by 256.
10 : DIVIDE_BY_512
Set blink rate divider to divide by 512.
11 : DIVIDE_BY_1024
Set blink rate divider to divide by 1024.
12 : DIVIDE_BY_2048
Set blink rate divider to divide by 2048.
13 : DIVIDE_BY_4096
Set blink rate divider to divide by 4096.
End of enumeration elements list.
Segment Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIASMD : Hardware Bias Mode.
bits : 0 - 0 (1 bit)
Enumeration:
0 : ONE_THIRD
Select 1/3 bias.
1 : ONE_HALF
Select 1/2 bias.
End of enumeration elements list.
SEGMD : Segment Mode.
bits : 1 - 2 (2 bit)
Enumeration:
0 : STATIC
Select static segment mode with one common COMn.0 used.
1 : 2_MUX
Select two-mux segment mode with two commons (COMn.0 and COMn.1) used.
2 : 3_MUX
Select three-mux segment mode with three commons (COMn.0, COMn.1, COMn.2) used.
3 : 4_MUX
Select four-mux segment mode with four commons (COMn.0, COMn.1, COMn.2 and COMn.3) used.
End of enumeration elements list.
BLANKEN : Segment Blank Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
Operate segments normally.
1 : ENABLED
Ground the segment pins regardless of the current LCD control state.
End of enumeration elements list.
RPHEN : Reset Phase Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DISABLED
Hardware switches the LCD segment and common pin controls directly from one state to another.
1 : ENABLED
Hardware switches the LCD segment and common pin controls to intermediate states for several RTC clock cycles before switching to the next state.
End of enumeration elements list.
RPHMD : Reset Phase Mode.
bits : 6 - 8 (3 bit)
Contrast Control
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRST : Contrast Voltage.
bits : 0 - 4 (5 bit)
CTRSTBF : Contrast Busy Flag.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
An update of the internal contrast registers is not in progress.
1 : SET
The internal contrast registers are busy updating.
End of enumeration elements list.
CPCDEN : Charge Pump Capacitor Divider Enable.
bits : 29 - 29 (1 bit)
Enumeration:
0 : DISABLED
Disable the charge pump capacitor divider.
1 : ENABLED
Enable the charge pump capacitor divider.
End of enumeration elements list.
VBAT Monitor Control
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBMTH : VBAT Monitor Threshold.
bits : 0 - 4 (5 bit)
VBMBF : VBAT Monitor Busy Flag.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
An update of the internal VBAT monitor registers is not in progress.
1 : SET
The internal VBAT monitor registers are busy updating.
End of enumeration elements list.
VBMCLKDIV : VBAT Monitor Clock Divider.
bits : 22 - 24 (3 bit)
VBMCDEN : VBAT Monitor Capacitor Divider Enable.
bits : 29 - 29 (1 bit)
Enumeration:
0 : DISABLED
Disable the VBAT monitor capacitor divider.
1 : ENABLED
Enable the VBAT monitor capacitor divider.
End of enumeration elements list.
VBMOEN : VBAT Monitor Offset Enable.
bits : 30 - 30 (1 bit)
Enumeration:
0 : DISABLED
The VBAT monitor threshold set by the VBMTH field functions as an absolute threshold value for the VBAT monitor.
1 : ENABLED
The VBAT monitor threshold set by the VBMTH field functions as an offset to the LCD contrast value set by CTRSTMD.
End of enumeration elements list.
VBMEN : VBAT Monitor Enable.
bits : 31 - 31 (1 bit)
Enumeration:
0 : DISABLED
Disable the VBAT monitor.
1 : ENABLED
Enable the VBAT monitor.
End of enumeration elements list.
Segment Mask 0
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEGEN : Segment Enable.
bits : 0 - 31 (32 bit)
Segment Mask 1
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEGEN : Segment Enable.
bits : 0 - 7 (8 bit)
Segment Data 0
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEGDATA0 : Segment LCDn.0 Control.
bits : 0 - 31 (32 bit)
Segment Data 1
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEGDATA1 : Segment LCDn.8 Control.
bits : 0 - 31 (32 bit)
Segment Data 2
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEGDATA2 : Segment LCDn.16 Control.
bits : 0 - 31 (32 bit)
Segment Data 3
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEGDATA3 : Segment LCDn.24 Control.
bits : 0 - 31 (32 bit)
Segment Data 4
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEGDATA4 : Segment LCDn.32 Control.
bits : 0 - 31 (32 bit)
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