Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Pulse Generator Counter.
bits : 0 - 11 (12 bit)
SSEL : Speed Select.
bits : 12 - 12 (1 bit)
Enumeration:
0 : NORMAL
The SSG module runs at normal speed, where each pulse and phase cycle consists of 16 ADC clocks.
1 : DOUBLE
The SSG module runs at double speed, where each pulse and phase cycle consists of 8 ADC clocks.
End of enumeration elements list.
PHGFREN : Phase Generator Free-Run Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
The Phase Generator runs only when pulse generation occurs.
1 : ENABLED
The Phase Generator runs when an ADC is enabled, regardless of the Pulse Generator settings.
End of enumeration elements list.
PUGFREN : Pulse Generator Free-Run Enable.
bits : 14 - 14 (1 bit)
Enumeration:
0 : DISABLED
The COUNT field determines the number of pulses generated by the Pulse Generator.
1 : ENABLED
The Pulse Generator always generates pulses regardless of COUNT unless all outputs are disabled (EX0EN, EX1EN, EX2EN, and EX3EN are all 0).
End of enumeration elements list.
Module Control
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EX0INVEN : Output 0 Invert Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : NORMAL
Do not invert the Pulse Generator output on EX0.
1 : INVERT
Invert the Pulse Generator output on EX0.
End of enumeration elements list.
EX1INVEN : Output 1 Invert Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : NORMAL
Do not invert the Pulse Generator output on EX1.
1 : INVERT
Invert the Pulse Generator output on EX1.
End of enumeration elements list.
EX2INVEN : Output 2 Invert Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : NORMAL
Do not invert the Pulse Generator output on EX2.
1 : INVERT
Invert the Pulse Generator output on EX2.
End of enumeration elements list.
EX3INVEN : Output 3 Invert Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NORMAL
Do not invert the Pulse Generator output on EX3.
1 : INVERT
Invert the Pulse Generator output on EX3.
End of enumeration elements list.
EX0EN : Output 0 Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
Disable the EX0 Pulse Generator output.
1 : ENABLED
Enable the EX0 Pulse Generator output.
End of enumeration elements list.
EX1EN : Output 1 Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DISABLED
Disable the EX1 Pulse Generator output.
1 : ENABLED
Enable the EX1 Pulse Generator output.
End of enumeration elements list.
EX2EN : Output 2 Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the EX2 Pulse Generator output.
1 : ENABLED
Enable the EX2 Pulse Generator output.
End of enumeration elements list.
EX3EN : Output 3 Enable.
bits : 7 - 7 (1 bit)
Enumeration:
0 : DISABLED
Disable the EX3 Pulse Generator output.
1 : ENABLED
Enable the EX3 Pulse Generator output.
End of enumeration elements list.
STATUS : SSG Module Status.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : IDLE
The SSG module is idle and the Pulse Generator is not operating.
1 : ACTIVE
The SSG module is active and the Pulse Generator is counting.
End of enumeration elements list.
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