\n

CRC_0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONTROL

DATA

RDATA


CONTROL

Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SINITEN SEED CRCEN POLYSEL BMDEN BBREN ORDER

SINITEN : Seed Initialization Enable.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : DISABLED

Do not initialize the CRC module to the value set by the SEED bit.

1 : ENABLED

Initialize the CRC module to the value set by the SEED bit.

End of enumeration elements list.

SEED : Seed Setting.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0 : ALL_ZEROES

CRC seed value is all 0's (0x00000000)

1 : ALL_ONES

CRC seed value is all 1's (0xFFFFFFFF).

End of enumeration elements list.

CRCEN : CRC Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : DISABLED

Disable CRC operations.

1 : ENABLED

Enable CRC operations.

End of enumeration elements list.

POLYSEL : Polynomial Selection.
bits : 4 - 5 (2 bit)

Enumeration:

0 : CRC_32_04C11DB7

Select 32-bit polynomial: 0x04C11DB7.

1 : CRC_16_1021

Select 16-bit polynomial: 0x1021.

2 : CRC_16_3D65

Select 16-bit polynomial: 0x3D65.

3 : CRC_16_8005

Select 16-bit polynomial: 0x8005.

End of enumeration elements list.

BMDEN : Byte Mode Enable.
bits : 8 - 8 (1 bit)

Enumeration:

0 : DISABLED

Disable byte mode (word/byte width is determined automatically by the hardware).

1 : ENABLED

Enable byte mode (all writes are considered as bytes).

End of enumeration elements list.

BBREN : Byte-Level Bit Reversal Enable.
bits : 9 - 9 (1 bit)

Enumeration:

0 : DISABLED

No byte-level bit reversal (input is same order as written).

1 : ENABLED

Byte-level bit reversal enabled (the bits in each byte are reversed).

End of enumeration elements list.

ORDER : Input Processing Order.
bits : 10 - 11 (2 bit)

Enumeration:

0 : NO_REORDER

No byte reorientation (output is same order as input).

1 : BIG_ENDIAN_16

Swap for 16-bit big endian order (input: B3 B2 B1 B0, output: B2 B3 B0 B1).

2 : BIG_ENDIAN_32

Swap for 32-bit big endian order (input: B3 B2 B1 B0, output: B0 B1 B2 B3).

End of enumeration elements list.


DATA

Input/Result Data
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Input/Result Data.
bits : 0 - 31 (32 bit)


RDATA

Bit-Reversed Output Data
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDATA RDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : Bit-Reversed Output Data.
bits : 0 - 31 (32 bit)
access : read-only



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