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Oscillators

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

DIVIDER

CONTROL

SSPR

CALCONFIG


DIVIDER

Reference Divider Setting
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIVIDER DIVIDER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M N

M : M Divider Value.
bits : 0 - 11 (12 bit)

N : N Divider Value.
bits : 16 - 27 (12 bit)


CONTROL

Module Control
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMTF HLMTF LCKI LMTIEN LCKIEN LCKPOL REFSEL LOCKTH STALL DITHEN EDGSEL OUTMD

LLMTF : CAL Saturation (Low) Flag.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

DCO period is not saturated low.

1 : SET

DCO period is saturated low.

End of enumeration elements list.

HLMTF : CAL Saturation (High) Flag.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

DCO period is not saturated high.

1 : SET

DCO period is saturated high.

End of enumeration elements list.

LCKI : Phase-Lock and Frequency-Lock Locked Interrupt Flag.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

DCO is disabled or not locked.

1 : SET

DCO is enabled and locked.

End of enumeration elements list.

LMTIEN : Limit Interrupt Enable.
bits : 9 - 9 (1 bit)

Enumeration:

0 : DISABLED

Saturation (high and low) interrupt disabled.

1 : ENABLED

Saturation (high and low) interrupt enabled.

End of enumeration elements list.

LCKIEN : Locked Interrupt Enable.
bits : 10 - 10 (1 bit)

Enumeration:

0 : DISABLED

The PLL locking does not cause an interrupt

1 : ENABLED

An interrupt is generated if LCKI matches the state selected by LCKPOL.

End of enumeration elements list.

LCKPOL : Lock Interrupt Polarity.
bits : 11 - 11 (1 bit)

Enumeration:

0 : ACTIVE_LOW

The lock state PLL interrupt will occur when LCKI is 0.

1 : ACTIVE_HIGH

The lock state PLL interrupt will occur when LCKI is 1.

End of enumeration elements list.

REFSEL : Reference Clock Selection Control.
bits : 16 - 17 (2 bit)

Enumeration:

0 : RTC0OSC

PLL reference clock (FREF) is the RTC0 oscillator (RTC0OSC).

1 : LPOSC0DIV

PLL reference clock (FREF) is the divided Low Power Oscillator (LPOSC0).

2 : EXTOSC0

PLL reference clock (FREF) is the external oscillator output (EXTOSC0).

3 : USBOSC0

PLL reference clock (FREF) is the USB0 oscillator (USB0OSC).

End of enumeration elements list.

LOCKTH : Lock Threshold Control.
bits : 20 - 21 (2 bit)

STALL : DCO Output Updates Stall.
bits : 26 - 26 (1 bit)

Enumeration:

0 : DISABLED

In phase-lock and frequency-lock modes, spectrum spreading, and dithering operate normally, if enabled.

1 : ENABLED

In phase-lock and frequency-lock modes, spectrum spreading, and dithering are prevented from updating the output of the DCO.

End of enumeration elements list.

DITHEN : Dithering Enable.
bits : 28 - 28 (1 bit)

Enumeration:

0 : DISABLED

Automatic DCO output dithering disabled.

1 : ENABLED

Automatic DCO output dithering enabled.

End of enumeration elements list.

EDGSEL : Edge Lock Select.
bits : 29 - 29 (1 bit)

Enumeration:

0 : FALLING_EDGE

Lock DCO output frequency to the falling edge of the reference frequency.

1 : RISING_EDGE

Lock DCO output frequency to the rising edge of the reference frequency.

End of enumeration elements list.

OUTMD : PLL Output Mode.
bits : 30 - 31 (2 bit)

Enumeration:

0 : OFF

DCO output is off.

1 : DCO

DCO output is in Free-Running DCO mode.

2 : FLL

DCO output is in frequency-lock mode (reference source required).

3 : PLL

DCO output is in phase-lock mode (reference source required).

End of enumeration elements list.


SSPR

Spectrum Spreading Control
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPR SSPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSAMP SSUINV

SSAMP : Spectrum Spreading Amplitude.
bits : 0 - 2 (3 bit)

Enumeration:

0 : DISABLED

Disable Spectrum Spreading.

1 : SETTING1

Spectrum Spreading set to approximately +/- 0.1% of TDCO.

2 : SETTING2

Spectrum Spreading set to approximately +/- 0.2% of TDCO.

3 : SETTING3

Spectrum Spreading set to approximately +/- 0.4% of TDCO.

4 : SETTING4

Spectrum Spreading set to approximately +/- 0.8% of TDCO.

5 : SETTING5

Spectrum Spreading set to approximately +/- 1.6% of TDCO.

End of enumeration elements list.

SSUINV : Spectrum Spreading Update Interval.
bits : 8 - 12 (5 bit)


CALCONFIG

Calibration Configuration
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALCONFIG CALCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CAL RANGE

DITHER : DCO Dither Setting.
bits : 0 - 3 (4 bit)

CAL : DCO Calibration Value.
bits : 4 - 15 (12 bit)

RANGE : DCO Range.
bits : 16 - 18 (3 bit)

Enumeration:

0 : RANGE0

DCO operates from 23 to 37 MHz.

1 : RANGE1

DCO operates from 33 to 54 MHz.

2 : RANGE2

DCO operates from 45 to 71 MHz.

3 : RANGE3

DCO operates from 53 to 80 MHz.

4 : RANGE4

DCO operates from 73 to 80 MHz.

End of enumeration elements list.



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