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PCA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

MODE_0

CONTROL_0

MODE

CONTROL

STATUS

COUNTER

LIMIT

CCAPV_0

CCAPVUPD_0

MODE_1

CONTROL_1

CCAPV_1

CCAPVUPD_1


MODE_0

Channel Capture/Compare Mode
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE_0 MODE_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COSEL PWMMD CMD

COSEL : Channel Output Function Select.
bits : 0 - 1 (2 bit)

Enumeration:

0 : TOGGLE_OUTPUT

Toggle the channel output at the next capture/compare, overflow, or intermediate event.

1 : SET_OUTPUT

Set the channel output at the next capture/compare, overflow, or intermediate event.

2 : CLEAR_OUTPUT

Clear the output at the next capture/compare, overflow, or intermediate event.

3 : NO_CHANGE

Capture/Compare, overflow, or intermediate events do not control the output state.

End of enumeration elements list.

PWMMD : PWM N-Bit Mode.
bits : 2 - 5 (4 bit)

CMD : Channel Operating Mode.
bits : 8 - 10 (3 bit)

Enumeration:

0 : EDGE_PWM

Configure the channel for edge-aligned PWM mode.

1 : CENTER_ALIGNED_PWM

Configure the channel for center-aligned PWM mode.

2 : HF_SQUARE_WAVE

Configure the channel for high-frequency/square-wave mode.

3 : TIMER_CAPTURE

Configure the channel for timer/capture mode.

4 : N_BIT_PWM

Configure the channel for n-bit edge-aligned PWM mode.

End of enumeration elements list.


CONTROL_0

Channel Capture/Compare Control
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL_0 CONTROL_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUTST CPCAPEN CNCAPEN CUPDCF CCIEN CIOVFIEN

COUTST : Channel Output State.
bits : 0 - 0 (1 bit)

Enumeration:

0 : LOW

The channel output state is low.

1 : HIGH

The channel output state is high.

End of enumeration elements list.

CPCAPEN : Positive Edge Input Capture Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : DISABLED

Disable positive-edge input capture.

1 : ENABLED

Enable positive-edge input capture.

End of enumeration elements list.

CNCAPEN : Negative Edge Input Capture Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : DISABLED

Disable negative-edge input capture.

1 : ENABLED

Enable negative-edge input capture.

End of enumeration elements list.

CUPDCF : Channel Register Update Complete Flag.
bits : 3 - 3 (1 bit)

Enumeration:

0 : NOT_SET

A PCA channel register update completed or is not pending.

1 : SET

A PCA channel register update has not completed and is still pending.

End of enumeration elements list.

CCIEN : Capture/Compare Interrupt Enable.
bits : 8 - 8 (1 bit)

Enumeration:

0 : DISABLED

Disable the channel capture/compare interrupt.

1 : ENABLED

Enable the channel capture/compare interrupt.

End of enumeration elements list.

CIOVFIEN : Intermediate Overflow Interrupt Enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : DISABLED

Disable the channel intermediate overflow interrupt.

1 : ENABLED

Enable the channel intermediate overflow interrupt.

End of enumeration elements list.


MODE

Module Operating Mode
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV CLKSEL

CLKDIV : Input Clock Divisor.
bits : 0 - 9 (10 bit)

CLKSEL : Input Clock (FCLKIN) Select.
bits : 10 - 12 (3 bit)

Enumeration:

0 : APB

Set the APB as the input clock (FCLKIN).

1 : TIMER0

Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN).

2 : HL_ECI

Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN).

3 : EXTOSCN

Set the external oscillator module output (EXTOSCn) divided by 2 as the input clock (FCLKIN).

4 : ECI

Set ECI transitions divided by 2 as the input clock (FCLKIN).

End of enumeration elements list.


CONTROL

Module Control
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVFIEN DBGMD DIVST DIV

OVFIEN : PCA Counter Overflow/Limit Interrupt Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : DISABLED

Disable the PCA counter overflow/limit event interrupt.

1 : ENABLED

Enable the PCA counter overflow/limit event interrupt.

End of enumeration elements list.

DBGMD : PCA Debug Mode.
bits : 6 - 6 (1 bit)

Enumeration:

0 : HALT

A debug breakpoint will cause the PCA to halt.

1 : RUN

The PCA will continue to operate while the core is halted in debug mode.

End of enumeration elements list.

DIVST : Clock Divider Output State.
bits : 21 - 21 (1 bit)

Enumeration:

0 : OUTPUT_HIGH

The clock divider is currently in the first half-cycle.

1 : OUTPUT_LOW

The clock divider is currently in the second half-cycle.

End of enumeration elements list.

DIV : Current Clock Divider Count.
bits : 22 - 31 (10 bit)


STATUS

Module Status
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0CCI C1CCI RUN OVFI C0IOVFI C1IOVFI

C0CCI : Channel 0 Capture/Compare Interrupt Flag.
bits : 0 - 0 (1 bit)

Enumeration:

0 : NOT_SET

A Channel 0 match or capture event did not occur.

1 : SET

A Channel 0 match or capture event occurred.

End of enumeration elements list.

C1CCI : Channel 1 Capture/Compare Interrupt Flag.
bits : 1 - 1 (1 bit)

Enumeration:

0 : NOT_SET

A Channel 1 match or capture event did not occur.

1 : SET

A Channel 1 match or capture event occurred.

End of enumeration elements list.

RUN : Counter/Timer Run.
bits : 6 - 6 (1 bit)

Enumeration:

0 : STOP

Stop the PCA Counter/Timer.

1 : START

Start the PCA Counter/Timer.

End of enumeration elements list.

OVFI : Counter/Timer Overflow/Limit Interrupt Flag.
bits : 7 - 7 (1 bit)

Enumeration:

0 : NOT_SET

A PCA Counter/Timer overflow/limit event did not occur.

1 : SET

A PCA Counter/Timer overflow/limit event occurred.

End of enumeration elements list.

C0IOVFI : Channel 0 Intermediate Overflow Interrupt Flag.
bits : 10 - 10 (1 bit)

Enumeration:

0 : NOT_SET

Channel 0 did not count past the channel n-bit mode limit.

1 : SET

Channel 0 counted past the channel n-bit mode limit.

End of enumeration elements list.

C1IOVFI : Channel 1 Intermediate Overflow Interrupt Flag.
bits : 11 - 11 (1 bit)

Enumeration:

0 : NOT_SET

Channel 1 did not count past the channel n-bit mode limit.

1 : SET

Channel 1 counted past the channel n-bit mode limit.

End of enumeration elements list.


COUNTER

Module Counter/Timer
address_offset : 0x1B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNTER COUNTER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNTER

COUNTER : Counter/Timer.
bits : 0 - 15 (16 bit)


LIMIT

Module Counter/Timer Upper Limit
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT LIMIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIMIT

LIMIT : Upper Limit.
bits : 0 - 15 (16 bit)


CCAPV_0

Channel Compare Value
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCAPV_0 CCAPV_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCAPV

CCAPV : Channel Compare Value.
bits : 0 - 17 (18 bit)


CCAPVUPD_0

Channel Compare Update Value
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCAPVUPD_0 CCAPVUPD_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCAPVUPD

CCAPVUPD : Channel Compare Update Value.
bits : 0 - 17 (18 bit)


MODE_1

Channel Capture/Compare Mode
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE_1 MODE_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COSEL PWMMD CMD

COSEL : Channel Output Function Select.
bits : 0 - 1 (2 bit)

Enumeration:

0 : TOGGLE_OUTPUT

Toggle the channel output at the next capture/compare, overflow, or intermediate event.

1 : SET_OUTPUT

Set the channel output at the next capture/compare, overflow, or intermediate event.

2 : CLEAR_OUTPUT

Clear the output at the next capture/compare, overflow, or intermediate event.

3 : NO_CHANGE

Capture/Compare, overflow, or intermediate events do not control the output state.

End of enumeration elements list.

PWMMD : PWM N-Bit Mode.
bits : 2 - 5 (4 bit)

CMD : Channel Operating Mode.
bits : 8 - 10 (3 bit)

Enumeration:

0 : EDGE_PWM

Configure the channel for edge-aligned PWM mode.

1 : CENTER_ALIGNED_PWM

Configure the channel for center-aligned PWM mode.

2 : HF_SQUARE_WAVE

Configure the channel for high-frequency/square-wave mode.

3 : TIMER_CAPTURE

Configure the channel for timer/capture mode.

4 : N_BIT_PWM

Configure the channel for n-bit edge-aligned PWM mode.

End of enumeration elements list.


CONTROL_1

Channel Capture/Compare Control
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL_1 CONTROL_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUTST CPCAPEN CNCAPEN CUPDCF CCIEN CIOVFIEN

COUTST : Channel Output State.
bits : 0 - 0 (1 bit)

Enumeration:

0 : LOW

The channel output state is low.

1 : HIGH

The channel output state is high.

End of enumeration elements list.

CPCAPEN : Positive Edge Input Capture Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : DISABLED

Disable positive-edge input capture.

1 : ENABLED

Enable positive-edge input capture.

End of enumeration elements list.

CNCAPEN : Negative Edge Input Capture Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : DISABLED

Disable negative-edge input capture.

1 : ENABLED

Enable negative-edge input capture.

End of enumeration elements list.

CUPDCF : Channel Register Update Complete Flag.
bits : 3 - 3 (1 bit)

Enumeration:

0 : NOT_SET

A PCA channel register update completed or is not pending.

1 : SET

A PCA channel register update has not completed and is still pending.

End of enumeration elements list.

CCIEN : Capture/Compare Interrupt Enable.
bits : 8 - 8 (1 bit)

Enumeration:

0 : DISABLED

Disable the channel capture/compare interrupt.

1 : ENABLED

Enable the channel capture/compare interrupt.

End of enumeration elements list.

CIOVFIEN : Intermediate Overflow Interrupt Enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : DISABLED

Disable the channel intermediate overflow interrupt.

1 : ENABLED

Enable the channel intermediate overflow interrupt.

End of enumeration elements list.


CCAPV_1

Channel Compare Value
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCAPV_1 CCAPV_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCAPV

CCAPV : Channel Compare Value.
bits : 0 - 17 (18 bit)


CCAPVUPD_1

Channel Compare Update Value
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCAPVUPD_1 CCAPVUPD_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCAPVUPD

CCAPVUPD : Channel Compare Update Value.
bits : 0 - 17 (18 bit)



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