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PBHD_4

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

PB

PBPIN

PBMDSEL

PBDEN

PBDRV

PBILIMIT

PBFSEL

PBSS

PBLOCK


PB

Output Latch
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB PB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB

PB : Output Latch.
bits : 0 - 5 (6 bit)


PBPIN

Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBPIN PBPIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBPIN

PBPIN : Pin Value.
bits : 0 - 5 (6 bit)
access : read-only


PBMDSEL

Mode Select
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBMDSEL PBMDSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBMDSEL

PBMDSEL : Mode Select.
bits : 0 - 5 (6 bit)


PBDEN

Driver Enable
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBDEN PBDEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBNDEN PBPDEN

PBNDEN : Port Bank N-Channel Driver Enable.
bits : 0 - 5 (6 bit)

PBPDEN : Port Bank P-Channel Driver Enable.
bits : 16 - 21 (6 bit)


PBDRV

Drive Strength
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBDRV PBDRV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBDRV PBPUEN PBLVMD PBSLEW PBBIASEN PBDRVEN PBVTRKEN

PBDRV : Drive Strength.
bits : 0 - 5 (6 bit)

PBPUEN : Port Bank Weak Pull-up Enable.
bits : 16 - 16 (1 bit)

Enumeration:

0 : DISABLED

Disable weak pull-ups for this port.

1 : ENABLED

Enable weak pull-ups for this port.

End of enumeration elements list.

PBLVMD : Port Low Voltage Mode.
bits : 17 - 17 (1 bit)

Enumeration:

0 : NORMAL

Port configured for normal mode.

1 : LOW

Port configured for low power mode.

End of enumeration elements list.

PBSLEW : Port Slew Control.
bits : 18 - 19 (2 bit)

Enumeration:

0 : FASTEST

Select the fastest transition speed for this port bank.

1 : FASTER

Select the faster transition speed for this port bank.

2 : SLOWER

Select the slower transition speed for this port bank.

3 : SLOWEST

Select the slowest transition speed for this port bank.

End of enumeration elements list.

PBBIASEN : Port Bias Enable.
bits : 21 - 21 (1 bit)

Enumeration:

0 : DISABLED

Disable the biasing to the port pins.

1 : ENABLED

Enable the biasing to the port pins.

End of enumeration elements list.

PBDRVEN : Port Drive Enable.
bits : 22 - 22 (1 bit)

Enumeration:

0 : DISABLED

Disable the port drivers.

1 : ENABLED

Enable the port drivers.

End of enumeration elements list.

PBVTRKEN : Port Voltage Supply Tracking Enable.
bits : 23 - 23 (1 bit)

Enumeration:

0 : DISABLED

Disable VIOHD tracking.

1 : ENABLED

Enable VIOHD tracking.

End of enumeration elements list.


PBILIMIT

Current Limit
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBILIMIT PBILIMIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBILEN NILIMIT PILIMIT

PBILEN : Current Limit Enable.
bits : 0 - 5 (6 bit)

NILIMIT : N-Channel Current Limit.
bits : 16 - 19 (4 bit)

Enumeration:

0 : MODE0

Set sink limit to mode 0.

1 : MODE1

Set sink limit to mode 1.

2 : MODE2

Set sink limit to mode 2.

3 : MODE3

Set sink limit to mode 3.

4 : MODE4

Set sink limit to mode 4.

5 : MODE5

Set sink limit to mode 5.

6 : MODE6

Set sink limit to mode 6.

7 : MODE7

Set sink limit to mode 7.

8 : MODE8

Set sink limit to mode 8.

9 : MODE9

Set sink limit to mode 9.

10 : MODE10

Set sink limit to mode 10.

11 : MODE11

Set sink limit to mode 11.

12 : MODE12

Set sink limit to mode 12.

13 : MODE13

Set sink limit to mode 13.

14 : MODE14

Set sink limit to mode 14.

15 : MODE15

Set sink limit to mode 15.

End of enumeration elements list.

PILIMIT : P-Channel Current Limit.
bits : 20 - 23 (4 bit)

Enumeration:

0 : MODE0

Set source limit to mode 0.

1 : MODE1

Set source limit to mode 1.

2 : MODE2

Set source limit to mode 2.

3 : MODE3

Set source limit to mode 3.

4 : MODE4

Set source limit to mode 4.

5 : MODE5

Set source limit to mode 5.

6 : MODE6

Set source limit to mode 6.

7 : MODE7

Set source limit to mode 7.

8 : MODE8

Set source limit to mode 8.

9 : MODE9

Set source limit to mode 9.

10 : MODE10

Set source limit to mode 10.

11 : MODE11

Set source limit to mode 11.

12 : MODE12

Set source limit to mode 12.

13 : MODE13

Set source limit to mode 13.

14 : MODE14

Set source limit to mode 14.

15 : MODE15

Set source limit to mode 15.

End of enumeration elements list.


PBFSEL

Function Select
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBFSEL PBFSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB0SEL PB1SEL PB2SEL PB3SEL PB4SEL PB5SEL

PB0SEL : Port Bank n.0 Function Select.
bits : 0 - 1 (2 bit)

Enumeration:

0 : GPIO

Pin configured for GPIO.

1 : PMLS

Pin configured for Port Mapped Level Shift.

2 : EPCA0

Pin configured for EPCA0 output.

3 : RESERVED

Reserved.

End of enumeration elements list.

PB1SEL : Port Bank n.1 Function Select.
bits : 2 - 3 (2 bit)

Enumeration:

0 : GPIO

Pin configured for GPIO.

1 : PMLS

Pin configured for Port Mapped Level Shift.

2 : EPCA0

Pin configured for EPCA0 output.

3 : RESERVED

Reserved.

End of enumeration elements list.

PB2SEL : Port Bank n.2 Function Select.
bits : 4 - 5 (2 bit)

Enumeration:

0 : GPIO

Pin configured for GPIO.

1 : PMLS

Pin configured for Port Mapped Level Shift.

2 : EPCA0

Pin configured for EPCA0 output.

3 : UART1

Pin configured for UART1 TX.

End of enumeration elements list.

PB3SEL : Port Bank n.3 Function Select.
bits : 6 - 7 (2 bit)

Enumeration:

0 : GPIO

Pin configured for GPIO.

1 : PMLS

Pin configured for Port Mapped Level Shift.

2 : EPCA0

Pin configured for EPCA0 output.

3 : UART1

Pin configured for UART1 RX.

End of enumeration elements list.

PB4SEL : Port Bank n.4 Function Select.
bits : 8 - 9 (2 bit)

Enumeration:

0 : GPIO

Pin configured for GPIO.

1 : PMLS

Pin configured for Port Mapped Level Shift.

2 : EPCA0

Pin configured for EPCA0 output.

3 : UART1

Pin configured for UART1 RTS.

End of enumeration elements list.

PB5SEL : Port Bank n.5 Function Select.
bits : 10 - 12 (3 bit)

Enumeration:

0 : GPIO

Pin configured for GPIO.

1 : PMLS

Pin configured for Port Mapped Level Shift.

2 : EPCA0

Pin configured for EPCA0 output.

3 : UART1

Pin configured for UART1 CTS.

4 : LPTIMER0

Pin configured for LPTIMER0 toggle output.

End of enumeration elements list.


PBSS

Safe State Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBSS PBSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB0SSSEL PB1SSSEL PB2SSSEL PB3SSSEL PB4SSSEL PB5SSSEL SSMDEN PBSSSMD

PB0SSSEL : Port Bank n.0 Safe State Select.
bits : 0 - 1 (2 bit)

Enumeration:

0 : HIZ

Place PBn.0 in a High Impedance state.

1 : HIGH

Drive PBn.0 High.

2 : LOW

Drive PBn.0 Low.

3 : DISABLED

Ignore the safe state signal (weak pull-ups disabled).

End of enumeration elements list.

PB1SSSEL : Port Bank n.1 Safe State Select.
bits : 2 - 3 (2 bit)

Enumeration:

0 : HIZ

Place PBn.1 in a High Impedance state.

1 : HIGH

Drive PBn.1 High.

2 : LOW

Drive PBn.1 Low.

3 : DISABLED

Ignore the safe state signal (weak pull-ups disabled).

End of enumeration elements list.

PB2SSSEL : Port Bank n.2 Safe State Select.
bits : 4 - 5 (2 bit)

Enumeration:

0 : HIZ

Place PBn.2 in a High Impedance state.

1 : HIGH

Drive PBn.2 High.

2 : LOW

Drive PBn.2 Low.

3 : DISABLED

Ignore the safe state signal (weak pull-ups disabled).

End of enumeration elements list.

PB3SSSEL : Port Bank n.3 Safe State Select.
bits : 6 - 7 (2 bit)

Enumeration:

0 : HIZ

Place PBn.3 in a High Impedance state.

1 : HIGH

Drive PBn.3 High.

2 : LOW

Drive PBn.3 Low.

3 : DISABLED

Ignore the safe state signal (weak pull-ups disabled).

End of enumeration elements list.

PB4SSSEL : Port Bank n.4 Safe State Select.
bits : 8 - 9 (2 bit)

Enumeration:

0 : HIZ

Place PBn.4 in a High Impedance state.

1 : HIGH

Drive PBn.4 High.

2 : LOW

Drive PBn.4 Low.

3 : DISABLED

Ignore the safe state signal (weak pull-ups disabled).

End of enumeration elements list.

PB5SSSEL : Port Bank n.5 Safe State Select.
bits : 10 - 11 (2 bit)

Enumeration:

0 : HIZ

Place PBn.5 in a High Impedance state.

1 : HIGH

Drive PBn.5 High.

2 : LOW

Drive PBn.5 Low.

3 : DISABLED

Ignore the safe state signal (weak pull-ups disabled).

End of enumeration elements list.

SSMDEN : Enter Safe State Mode.
bits : 16 - 16 (1 bit)

Enumeration:

0 : DISABLED

Disable Safe State.

1 : ENABLED

Enter Safe State. Each PBn.x pin will enter the states defined by PBxSSSEL.

End of enumeration elements list.

PBSSSMD : Safe State Signal Mode.
bits : 17 - 17 (1 bit)

Enumeration:

0 : DEGLITCH

Enable deglitching on the kill signal input. The kill signal must be asserted for two APB clocks to be recognized.

1 : IMMEDIATE

Disable deglitching on the kill signal input. The kill signal will take immediate effect.

End of enumeration elements list.


PBLOCK

Lock Control
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBLOCK PBLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBLOCK

PBLOCK : Port Bank Lock.
bits : 0 - 5 (6 bit)



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