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FDCAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CREL

TEST

CKDIV

RWD

CCCR

NBTP

TSCC

TSCV

TOCC

TOCV

ENDN

ECR

PSR

TDCR

IR

IE

ILS

ILE

RXGFC

XIDAM

HPMS

RXF0S

RXF0A

RXF1S

RXF1A

DBTP

TXBC

TXFQS

TXBRP

TXBAR

TXBCR

TXBTO

TXBCF

TXBTIE

TXBCIE

TXEFS

TXEFA


CREL

FDCAN Core Release Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CREL CREL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY MON YEAR SUBSTEP STEP REL

DAY : DAY
bits : 0 - 7 (8 bit)

MON : MON
bits : 8 - 15 (8 bit)

YEAR : YEAR
bits : 16 - 19 (4 bit)

SUBSTEP : SUBSTEP
bits : 20 - 23 (4 bit)

STEP : STEP
bits : 24 - 27 (4 bit)

REL : REL
bits : 28 - 31 (4 bit)


TEST

Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBCK TX RX

LBCK : LBCK
bits : 4 - 4 (1 bit)

TX : TX
bits : 5 - 6 (2 bit)

RX : RX
bits : 7 - 7 (1 bit)


CKDIV

FDCAN CFG clock divider register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKDIV CKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIV

PDIV : input clock divider. the APB clock could be divided prior to be used by the CAN sub
bits : 0 - 3 (4 bit)


RWD

The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RWD RWD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDC WDV

WDC : WDC
bits : 0 - 7 (8 bit)
access : read-write

WDV : WDV
bits : 8 - 15 (8 bit)
access : read-only


CCCR

For details about setting and resetting of single bits see Software initialization.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCCR CCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT CCE ASM CSA CSR MON DAR TEST FDOE BRSE PXHD EFBI TXP NISO

INIT : INIT
bits : 0 - 0 (1 bit)

CCE : CCE
bits : 1 - 1 (1 bit)

ASM : ASM
bits : 2 - 2 (1 bit)

CSA : CSA
bits : 3 - 3 (1 bit)

CSR : CSR
bits : 4 - 4 (1 bit)

MON : MON
bits : 5 - 5 (1 bit)

DAR : DAR
bits : 6 - 6 (1 bit)

TEST : TEST
bits : 7 - 7 (1 bit)

FDOE : FDOE
bits : 8 - 8 (1 bit)

BRSE : BRSE
bits : 9 - 9 (1 bit)

PXHD : PXHD
bits : 12 - 12 (1 bit)

EFBI : EFBI
bits : 13 - 13 (1 bit)

TXP : TXP
bits : 14 - 14 (1 bit)

NISO : NISO
bits : 15 - 15 (1 bit)


NBTP

FDCAN_NBTP
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NBTP NBTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSEG2 NTSEG1 NBRP NSJW

TSEG2 : TSEG2
bits : 0 - 6 (7 bit)

NTSEG1 : NTSEG1
bits : 8 - 15 (8 bit)

NBRP : NBRP
bits : 16 - 24 (9 bit)

NSJW : NSJW
bits : 25 - 31 (7 bit)


TSCC

FDCAN Timestamp Counter Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSCC TSCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSS TCP

TSS : TSS
bits : 0 - 1 (2 bit)

TCP : TCP
bits : 16 - 19 (4 bit)


TSCV

FDCAN Timestamp Counter Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSCV TSCV read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSC

TSC : TSC
bits : 0 - 15 (16 bit)


TOCC

FDCAN Timeout Counter Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOCC TOCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETOC TOS TOP

ETOC : ETOC
bits : 0 - 0 (1 bit)
access : read-write

TOS : TOS
bits : 1 - 2 (2 bit)
access : write-only

TOP : TOP
bits : 16 - 31 (16 bit)
access : read-write


TOCV

FDCAN Timeout Counter Value Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TOCV TOCV read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOC

TOC : TOC
bits : 0 - 15 (16 bit)


ENDN

FDCAN Core Release Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENDN ENDN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETV

ETV : ETV
bits : 0 - 31 (32 bit)


ECR

FDCAN Error Counter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECR ECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEC TREC RP CEL

TEC : TEC
bits : 0 - 7 (8 bit)

TREC : TREC
bits : 8 - 14 (7 bit)

RP : RP
bits : 15 - 15 (1 bit)

CEL : CEL
bits : 16 - 23 (8 bit)


PSR

FDCAN Protocol Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEC ACT EP EW BO DLEC RESI RBRS REDL PXE TDCV

LEC : LEC
bits : 0 - 2 (3 bit)
access : read-write

ACT : ACT
bits : 3 - 4 (2 bit)
access : write-only

EP : EP
bits : 5 - 5 (1 bit)
access : read-write

EW : EW
bits : 6 - 6 (1 bit)
access : read-write

BO : BO
bits : 7 - 7 (1 bit)
access : read-write

DLEC : DLEC
bits : 8 - 10 (3 bit)
access : write-only

RESI : RESI
bits : 11 - 11 (1 bit)
access : read-write

RBRS : RBRS
bits : 12 - 12 (1 bit)
access : read-write

REDL : REDL
bits : 13 - 13 (1 bit)
access : read-write

PXE : PXE
bits : 14 - 14 (1 bit)
access : read-write

TDCV : TDCV
bits : 16 - 22 (7 bit)
access : read-write


TDCR

FDCAN Transmitter Delay Compensation Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDCR TDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDCF TDCO

TDCF : TDCF
bits : 0 - 6 (7 bit)

TDCO : TDCO
bits : 8 - 14 (7 bit)


IR

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IR IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0N RF0W RF0F RF0L RF1N RF1W RF1F RF1L HPM TC TCF TFE TEFN TEFW TEFF TEFL TSW MRAF TOO DRX ELO EP EW BO WDI PEA PED ARA

RF0N : RF0N
bits : 0 - 0 (1 bit)

RF0W : RF0W
bits : 1 - 1 (1 bit)

RF0F : RF0F
bits : 2 - 2 (1 bit)

RF0L : RF0L
bits : 3 - 3 (1 bit)

RF1N : RF1N
bits : 4 - 4 (1 bit)

RF1W : RF1W
bits : 5 - 5 (1 bit)

RF1F : RF1F
bits : 6 - 6 (1 bit)

RF1L : RF1L
bits : 7 - 7 (1 bit)

HPM : HPM
bits : 8 - 8 (1 bit)

TC : TC
bits : 9 - 9 (1 bit)

TCF : TCF
bits : 10 - 10 (1 bit)

TFE : TFE
bits : 11 - 11 (1 bit)

TEFN : TEFN
bits : 12 - 12 (1 bit)

TEFW : TEFW
bits : 13 - 13 (1 bit)

TEFF : TEFF
bits : 14 - 14 (1 bit)

TEFL : TEFL
bits : 15 - 15 (1 bit)

TSW : TSW
bits : 16 - 16 (1 bit)

MRAF : MRAF
bits : 17 - 17 (1 bit)

TOO : TOO
bits : 18 - 18 (1 bit)

DRX : DRX
bits : 19 - 19 (1 bit)

ELO : ELO
bits : 22 - 22 (1 bit)

EP : EP
bits : 23 - 23 (1 bit)

EW : EW
bits : 24 - 24 (1 bit)

BO : BO
bits : 25 - 25 (1 bit)

WDI : WDI
bits : 26 - 26 (1 bit)

PEA : PEA
bits : 27 - 27 (1 bit)

PED : PED
bits : 28 - 28 (1 bit)

ARA : ARA
bits : 29 - 29 (1 bit)


IE

The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0NE RF0WE RF0FE RF0LE RF1NE RF1WE RF1FE RF1LE HPME TCE TCFE TFEE TEFNE TEFWE TEFFE TEFLE TSWE MRAFE TOOE DRX BECE BEUE ELOE EPE EWE BOE WDIE PEAE PEDE ARAE

RF0NE : RF0NE
bits : 0 - 0 (1 bit)

RF0WE : RF0WE
bits : 1 - 1 (1 bit)

RF0FE : RF0FE
bits : 2 - 2 (1 bit)

RF0LE : RF0LE
bits : 3 - 3 (1 bit)

RF1NE : RF1NE
bits : 4 - 4 (1 bit)

RF1WE : RF1WE
bits : 5 - 5 (1 bit)

RF1FE : RF1FE
bits : 6 - 6 (1 bit)

RF1LE : RF1LE
bits : 7 - 7 (1 bit)

HPME : HPME
bits : 8 - 8 (1 bit)

TCE : TCE
bits : 9 - 9 (1 bit)

TCFE : TCFE
bits : 10 - 10 (1 bit)

TFEE : TFEE
bits : 11 - 11 (1 bit)

TEFNE : TEFNE
bits : 12 - 12 (1 bit)

TEFWE : TEFWE
bits : 13 - 13 (1 bit)

TEFFE : TEFFE
bits : 14 - 14 (1 bit)

TEFLE : TEFLE
bits : 15 - 15 (1 bit)

TSWE : TSWE
bits : 16 - 16 (1 bit)

MRAFE : MRAFE
bits : 17 - 17 (1 bit)

TOOE : TOOE
bits : 18 - 18 (1 bit)

DRX : DRX
bits : 19 - 19 (1 bit)

BECE : BECE
bits : 20 - 20 (1 bit)

BEUE : BEUE
bits : 21 - 21 (1 bit)

ELOE : ELOE
bits : 22 - 22 (1 bit)

EPE : EPE
bits : 23 - 23 (1 bit)

EWE : EWE
bits : 24 - 24 (1 bit)

BOE : BOE
bits : 25 - 25 (1 bit)

WDIE : WDIE
bits : 26 - 26 (1 bit)

PEAE : PEAE
bits : 27 - 27 (1 bit)

PEDE : PEDE
bits : 28 - 28 (1 bit)

ARAE : ARAE
bits : 29 - 29 (1 bit)


ILS

The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ILS ILS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0NL RF0WL RF0FL RF0LL RF1NL RF1WL RF1FL RF1LL HPML TCL TCFL TFEL TEFNL TEFWL TEFFL TEFLL TSWL MRAFL TOOL DRXL BECL BEUL ELOL EPL EWL BOL WDIL PEAL PEDL ARAL

RF0NL : RF0NL
bits : 0 - 0 (1 bit)

RF0WL : RF0WL
bits : 1 - 1 (1 bit)

RF0FL : RF0FL
bits : 2 - 2 (1 bit)

RF0LL : RF0LL
bits : 3 - 3 (1 bit)

RF1NL : RF1NL
bits : 4 - 4 (1 bit)

RF1WL : RF1WL
bits : 5 - 5 (1 bit)

RF1FL : RF1FL
bits : 6 - 6 (1 bit)

RF1LL : RF1LL
bits : 7 - 7 (1 bit)

HPML : HPML
bits : 8 - 8 (1 bit)

TCL : TCL
bits : 9 - 9 (1 bit)

TCFL : TCFL
bits : 10 - 10 (1 bit)

TFEL : TFEL
bits : 11 - 11 (1 bit)

TEFNL : TEFNL
bits : 12 - 12 (1 bit)

TEFWL : TEFWL
bits : 13 - 13 (1 bit)

TEFFL : TEFFL
bits : 14 - 14 (1 bit)

TEFLL : TEFLL
bits : 15 - 15 (1 bit)

TSWL : TSWL
bits : 16 - 16 (1 bit)

MRAFL : MRAFL
bits : 17 - 17 (1 bit)

TOOL : TOOL
bits : 18 - 18 (1 bit)

DRXL : DRXL
bits : 19 - 19 (1 bit)

BECL : BECL
bits : 20 - 20 (1 bit)

BEUL : BEUL
bits : 21 - 21 (1 bit)

ELOL : ELOL
bits : 22 - 22 (1 bit)

EPL : EPL
bits : 23 - 23 (1 bit)

EWL : EWL
bits : 24 - 24 (1 bit)

BOL : BOL
bits : 25 - 25 (1 bit)

WDIL : WDIL
bits : 26 - 26 (1 bit)

PEAL : PEAL
bits : 27 - 27 (1 bit)

PEDL : PEDL
bits : 28 - 28 (1 bit)

ARAL : ARAL
bits : 29 - 29 (1 bit)


ILE

Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ILE ILE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EINT0 EINT1

EINT0 : EINT0
bits : 0 - 0 (1 bit)

EINT1 : EINT1
bits : 1 - 1 (1 bit)


RXGFC

Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXGFC RXGFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRFE RRFS ANFE ANFS

RRFE : RRFE
bits : 0 - 0 (1 bit)
access : read-write

RRFS : RRFS
bits : 1 - 1 (1 bit)
access : read-write

ANFE : ANFE
bits : 2 - 3 (2 bit)
access : write-only

ANFS : ANFS
bits : 4 - 5 (2 bit)
access : write-only


XIDAM

FDCAN Extended ID and Mask Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XIDAM XIDAM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIDM

EIDM : EIDM
bits : 0 - 28 (29 bit)


HPMS

This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HPMS HPMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIDX MSI FIDX FLST

BIDX : BIDX
bits : 0 - 5 (6 bit)

MSI : MSI
bits : 6 - 7 (2 bit)

FIDX : FIDX
bits : 8 - 14 (7 bit)

FLST : FLST
bits : 15 - 15 (1 bit)


RXF0S

FDCAN Rx FIFO 0 Status Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXF0S RXF0S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0FL F0GI F0PI F0F RF0L

F0FL : F0FL
bits : 0 - 6 (7 bit)

F0GI : F0GI
bits : 8 - 13 (6 bit)

F0PI : F0PI
bits : 16 - 21 (6 bit)

F0F : F0F
bits : 24 - 24 (1 bit)

RF0L : RF0L
bits : 25 - 25 (1 bit)


RXF0A

CAN Rx FIFO 0 Acknowledge Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXF0A RXF0A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0AI

F0AI : F0AI
bits : 0 - 5 (6 bit)


RXF1S

FDCAN Rx FIFO 1 Status Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXF1S RXF1S read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1FL F1GI F1PI F1F RF1L DMS

F1FL : F1FL
bits : 0 - 6 (7 bit)

F1GI : F1GI
bits : 8 - 13 (6 bit)

F1PI : F1PI
bits : 16 - 21 (6 bit)

F1F : F1F
bits : 24 - 24 (1 bit)

RF1L : RF1L
bits : 25 - 25 (1 bit)

DMS : DMS
bits : 30 - 31 (2 bit)


RXF1A

FDCAN Rx FIFO 1 Acknowledge Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXF1A RXF1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1AI

F1AI : F1AI
bits : 0 - 5 (6 bit)


DBTP

This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBTP DBTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSJW DTSEG2 DTSEG1 DBRP TDC

DSJW : DSJW
bits : 0 - 3 (4 bit)
access : read-write

DTSEG2 : DTSEG2
bits : 4 - 7 (4 bit)
access : read-write

DTSEG1 : DTSEG1
bits : 8 - 12 (5 bit)
access : write-only

DBRP : DBRP
bits : 16 - 20 (5 bit)
access : read-write

TDC : TDC
bits : 23 - 23 (1 bit)
access : read-only


TXBC

FDCAN Tx Buffer Configuration Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXBC TXBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBSA NDTB TFQS TFQM

TBSA : TBSA
bits : 2 - 15 (14 bit)

NDTB : NDTB
bits : 16 - 21 (6 bit)

TFQS : TFQS
bits : 24 - 29 (6 bit)

TFQM : TFQM
bits : 30 - 30 (1 bit)


TXFQS

The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXFQS TXFQS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFFL TFGI TFQPI TFQF

TFFL : TFFL
bits : 0 - 5 (6 bit)

TFGI : TFGI
bits : 8 - 12 (5 bit)

TFQPI : TFQPI
bits : 16 - 20 (5 bit)

TFQF : TFQF
bits : 21 - 21 (1 bit)


TXBRP

FDCAN Tx Buffer Request Pending Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXBRP TXBRP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRP

TRP : TRP
bits : 0 - 31 (32 bit)


TXBAR

FDCAN Tx Buffer Add Request Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXBAR TXBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR

AR : AR
bits : 0 - 31 (32 bit)


TXBCR

FDCAN Tx Buffer Cancellation Request Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXBCR TXBCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR

CR : CR
bits : 0 - 31 (32 bit)


TXBTO

FDCAN Tx Buffer Transmission Occurred Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXBTO TXBTO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO

TO : TO
bits : 0 - 31 (32 bit)


TXBCF

FDCAN Tx Buffer Cancellation Finished Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXBCF TXBCF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF

CF : CF
bits : 0 - 31 (32 bit)


TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXBTIE TXBTIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE

TIE : TIE
bits : 0 - 31 (32 bit)


TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXBCIE TXBCIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFIE

CFIE : CFIE
bits : 0 - 31 (32 bit)


TXEFS

FDCAN Tx Event FIFO Status Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXEFS TXEFS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFFL EFGI EFPI EFF TEFL

EFFL : EFFL
bits : 0 - 5 (6 bit)

EFGI : EFGI
bits : 8 - 12 (5 bit)

EFPI : EFPI
bits : 16 - 20 (5 bit)

EFF : EFF
bits : 24 - 24 (1 bit)

TEFL : TEFL
bits : 25 - 25 (1 bit)


TXEFA

FDCAN Tx Event FIFO Acknowledge Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXEFA TXEFA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFAI

EFAI : EFAI
bits : 0 - 4 (5 bit)



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