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address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Active Width Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AAH : Accumulated Active Height (in units of horizontal scan line)
bits : 0 - 10 (11 bit)
AAV : AAV
bits : 16 - 27 (12 bit)
Layerx Control Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Layer Enable
bits : 0 - 0 (1 bit)
COLKEN : Color Keying Enable
bits : 1 - 1 (1 bit)
CLUTEN : Color Look-Up Table Enable
bits : 4 - 4 (1 bit)
Layerx Window Horizontal Position Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WHSTPOS : Window Horizontal Start Position
bits : 0 - 11 (12 bit)
WHSPPOS : Window Horizontal Stop Position
bits : 16 - 27 (12 bit)
Layerx Window Vertical Position Configuration Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WVSTPOS : Window Vertical Start Position
bits : 0 - 10 (11 bit)
WVSPPOS : Window Vertical Stop Position
bits : 16 - 26 (11 bit)
Layerx Color Keying Configuration Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKBLUE : Color Key Blue value
bits : 0 - 7 (8 bit)
CKGREEN : Color Key Green value
bits : 8 - 15 (8 bit)
CKRED : Color Key Red value
bits : 16 - 23 (8 bit)
Layerx Pixel Format Configuration Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF : Pixel Format
bits : 0 - 2 (3 bit)
Layerx Constant Alpha Configuration Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONSTA : Constant Alpha
bits : 0 - 7 (8 bit)
Layerx Default Color Configuration Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCBLUE : Default Color Blue
bits : 0 - 7 (8 bit)
DCGREEN : Default Color Green
bits : 8 - 15 (8 bit)
DCRED : Default Color Red
bits : 16 - 23 (8 bit)
DCALPHA : Default Color Alpha
bits : 24 - 31 (8 bit)
Layerx Blending Factors Configuration Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BF2 : Blending Factor 2
bits : 0 - 2 (3 bit)
BF1 : Blending Factor 1
bits : 8 - 10 (3 bit)
Layerx Color Frame Buffer Address Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBADD : Color Frame Buffer Start Address
bits : 0 - 31 (32 bit)
Layerx Color Frame Buffer Length Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBLL : Color Frame Buffer Line Length
bits : 0 - 12 (13 bit)
CFBP : Color Frame Buffer Pitch in bytes
bits : 16 - 28 (13 bit)
Layerx ColorFrame Buffer Line Number Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBLNBR : Frame Buffer Line Number
bits : 0 - 10 (11 bit)
Total Width Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOTALH : Total Height (in units of horizontal scan line)
bits : 0 - 10 (11 bit)
TOTALW : Total Width (in units of pixel clock period)
bits : 16 - 27 (12 bit)
Layerx CLUT Write Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BLUE : Blue value
bits : 0 - 7 (8 bit)
GREEN : Green value
bits : 8 - 15 (8 bit)
RED : Red value
bits : 16 - 23 (8 bit)
CLUTADD : CLUT Address
bits : 24 - 31 (8 bit)
Global Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCEN : LCD-TFT controller enable bit
bits : 0 - 0 (1 bit)
access : read-write
DBW : Dither Blue Width
bits : 4 - 6 (3 bit)
access : read-only
DGW : Dither Green Width
bits : 8 - 10 (3 bit)
access : read-only
DRW : Dither Red Width
bits : 12 - 14 (3 bit)
access : read-only
DEN : Dither Enable
bits : 16 - 16 (1 bit)
access : read-write
PCPOL : Pixel Clock Polarity
bits : 28 - 28 (1 bit)
access : read-write
DEPOL : Data Enable Polarity
bits : 29 - 29 (1 bit)
access : read-write
VSPOL : Vertical Synchronization Polarity
bits : 30 - 30 (1 bit)
access : read-write
HSPOL : Horizontal Synchronization Polarity
bits : 31 - 31 (1 bit)
access : read-write
Shadow Reload Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR : Immediate Reload
bits : 0 - 0 (1 bit)
VBR : Vertical Blanking Reload
bits : 1 - 1 (1 bit)
Background Color Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCBLUE : Background Color Blue value
bits : 0 - 7 (8 bit)
BCGREEN : Background Color Green value
bits : 8 - 15 (8 bit)
BCRED : Background Color Red value
bits : 16 - 23 (8 bit)
Interrupt Enable Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIE : Line Interrupt Enable
bits : 0 - 0 (1 bit)
FUIE : FIFO Underrun Interrupt Enable
bits : 1 - 1 (1 bit)
TERRIE : Transfer Error Interrupt Enable
bits : 2 - 2 (1 bit)
RRIE : Register Reload interrupt enable
bits : 3 - 3 (1 bit)
Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LIF : Line Interrupt flag
bits : 0 - 0 (1 bit)
FUIF : FIFO Underrun Interrupt flag
bits : 1 - 1 (1 bit)
TERRIF : Transfer Error interrupt flag
bits : 2 - 2 (1 bit)
RRIF : Register Reload Interrupt Flag
bits : 3 - 3 (1 bit)
Interrupt Clear Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLIF : Clears the Line Interrupt Flag
bits : 0 - 0 (1 bit)
CFUIF : Clears the FIFO Underrun Interrupt flag
bits : 1 - 1 (1 bit)
CTERRIF : Clears the Transfer Error Interrupt Flag
bits : 2 - 2 (1 bit)
CRRIF : Clears Register Reload Interrupt Flag
bits : 3 - 3 (1 bit)
Line Interrupt Position Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIPOS : Line Interrupt Position
bits : 0 - 10 (11 bit)
Current Position Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CYPOS : Current Y Position
bits : 0 - 15 (16 bit)
CXPOS : Current X Position
bits : 16 - 31 (16 bit)
Current Display Status Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VDES : Vertical Data Enable display Status
bits : 0 - 0 (1 bit)
HDES : Horizontal Data Enable display Status
bits : 1 - 1 (1 bit)
VSYNCS : Vertical Synchronization display Status
bits : 2 - 2 (1 bit)
HSYNCS : Horizontal Synchronization display Status
bits : 3 - 3 (1 bit)
Synchronization Size Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSH : Vertical Synchronization Height (in units of horizontal scan line)
bits : 0 - 10 (11 bit)
HSW : Horizontal Synchronization Width (in units of pixel clock period)
bits : 16 - 25 (10 bit)
Layerx Control Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Layer Enable
bits : 0 - 0 (1 bit)
COLKEN : Color Keying Enable
bits : 1 - 1 (1 bit)
CLUTEN : Color Look-Up Table Enable
bits : 4 - 4 (1 bit)
Layerx Window Horizontal Position Configuration Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WHSTPOS : Window Horizontal Start Position
bits : 0 - 11 (12 bit)
WHSPPOS : Window Horizontal Stop Position
bits : 16 - 27 (12 bit)
Layerx Window Vertical Position Configuration Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WVSTPOS : Window Vertical Start Position
bits : 0 - 10 (11 bit)
WVSPPOS : Window Vertical Stop Position
bits : 16 - 26 (11 bit)
Layerx Color Keying Configuration Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKBLUE : Color Key Blue value
bits : 0 - 7 (8 bit)
CKGREEN : Color Key Green value
bits : 8 - 15 (8 bit)
CKRED : Color Key Red value
bits : 16 - 23 (8 bit)
Layerx Pixel Format Configuration Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF : Pixel Format
bits : 0 - 2 (3 bit)
Layerx Constant Alpha Configuration Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONSTA : Constant Alpha
bits : 0 - 7 (8 bit)
Layerx Default Color Configuration Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCBLUE : Default Color Blue
bits : 0 - 7 (8 bit)
DCGREEN : Default Color Green
bits : 8 - 15 (8 bit)
DCRED : Default Color Red
bits : 16 - 23 (8 bit)
DCALPHA : Default Color Alpha
bits : 24 - 31 (8 bit)
Layerx Blending Factors Configuration Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BF2 : Blending Factor 2
bits : 0 - 2 (3 bit)
BF1 : Blending Factor 1
bits : 8 - 10 (3 bit)
Layerx Color Frame Buffer Address Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBADD : Color Frame Buffer Start Address
bits : 0 - 31 (32 bit)
Layerx Color Frame Buffer Length Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBLL : Color Frame Buffer Line Length
bits : 0 - 12 (13 bit)
CFBP : Color Frame Buffer Pitch in bytes
bits : 16 - 28 (13 bit)
Layerx ColorFrame Buffer Line Number Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBLNBR : Frame Buffer Line Number
bits : 0 - 10 (11 bit)
Back Porch Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AVBP : Accumulated Vertical back porch (in units of horizontal scan line)
bits : 0 - 10 (11 bit)
AHBP : Accumulated Horizontal back porch (in units of pixel clock period)
bits : 16 - 27 (12 bit)
Layerx CLUT Write Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BLUE : Blue value
bits : 0 - 7 (8 bit)
GREEN : Green value
bits : 8 - 15 (8 bit)
RED : Red value
bits : 16 - 23 (8 bit)
CLUTADD : CLUT Address
bits : 24 - 31 (8 bit)
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