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UDFS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

Registers

INTSTS

MSTSET

DMACRDREQ

DMACRDVL

UDC2RDREQ

UDC2RDVL

ARBTSET

INTENB

MWSADR

MWEADR

MWCADR

MWAHBADR

MRSADR

MREADR

MRCADR

MRAHBADR

MWTOUT

PWCTL

MSTSTS

TOUTCNT

C2STSET


INTSTS

Interrupt Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTS INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SETUP INT_STATUS_NAK INT_STATUS INT_RX_ZERO INT_SOF INT_EP0 INT_EP INT_NAK INT_SUSPEND_RESUME INT_USB_RESET INT_USB_RESET_END INT_MW_SET_ADD INT_MW_END_ADD INT_MW_TIMEOUT INT_MW_AHBERR INT_MR_END_ADD INT_MR_EP_DSET INT_MR_AHBERR INT_UDC2_REG_RD INT_DMAC_REG_RD INT_POWERDETECT INT_MW_RERROR

INT_SETUP : INT_SETUP
bits : 0 - 0 (1 bit)
access : read-only

INT_STATUS_NAK : INT_STATUS_NAK
bits : 1 - 1 (1 bit)
access : read-only

INT_STATUS : INT_STATUS
bits : 2 - 2 (1 bit)
access : read-only

INT_RX_ZERO : INT_RX_ZERO
bits : 3 - 3 (1 bit)
access : read-only

INT_SOF : INT_SOF
bits : 4 - 4 (1 bit)
access : read-only

INT_EP0 : INT_EP0
bits : 5 - 5 (1 bit)
access : read-only

INT_EP : INT_EP
bits : 6 - 6 (1 bit)
access : read-only

INT_NAK : INT_NAK
bits : 7 - 7 (1 bit)
access : read-only

INT_SUSPEND_RESUME : INT_SUSPEND_RESUME
bits : 8 - 8 (1 bit)
access : read-write

INT_USB_RESET : INT_USB_RESET
bits : 9 - 9 (1 bit)
access : read-write

INT_USB_RESET_END : INT_USB_RESET_END
bits : 10 - 10 (1 bit)
access : read-write

INT_MW_SET_ADD : INT_MW_SET_ADD
bits : 17 - 17 (1 bit)
access : read-write

INT_MW_END_ADD : INT_MW_END_ADD
bits : 18 - 18 (1 bit)
access : read-write

INT_MW_TIMEOUT : INT_MW_TIMEOUT
bits : 19 - 19 (1 bit)
access : read-write

INT_MW_AHBERR : INT_MW_AHBERR
bits : 20 - 20 (1 bit)
access : read-write

INT_MR_END_ADD : INT_MR_END_ADD
bits : 21 - 21 (1 bit)
access : read-write

INT_MR_EP_DSET : INT_MR_EP_DSET
bits : 22 - 22 (1 bit)
access : read-write

INT_MR_AHBERR : INT_MR_AHBERR
bits : 23 - 23 (1 bit)
access : read-write

INT_UDC2_REG_RD : INT_UDC2_REG_RD
bits : 24 - 24 (1 bit)
access : read-write

INT_DMAC_REG_RD : INT_DMAC_REG_RD
bits : 25 - 25 (1 bit)
access : read-write

INT_POWERDETECT : INT_POWERDETECT
bits : 28 - 28 (1 bit)
access : read-write

INT_MW_RERROR : INT_MW_RERROR
bits : 29 - 29 (1 bit)
access : read-write


MSTSET

DMAC setting
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSTSET MSTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MW_ENABLE MW_ABORT MW_RESET MR_ENABLE MR_ABORT MR_RESET M_BURST_TYPE

MW_ENABLE : MW_ENABLE
bits : 0 - 0 (1 bit)
access : read-write

MW_ABORT : MW_ABORT
bits : 1 - 1 (1 bit)
access : write-only

MW_RESET : MW_RESET
bits : 2 - 2 (1 bit)
access : read-write

MR_ENABLE : MR_ENABLE
bits : 4 - 4 (1 bit)
access : read-write

MR_ABORT : MR_ABORT
bits : 5 - 5 (1 bit)
access : write-only

MR_RESET : MR_RESET
bits : 6 - 6 (1 bit)
access : read-write

M_BURST_TYPE : M_BURST_TYPE
bits : 8 - 8 (1 bit)
access : read-write


DMACRDREQ

DMAC Read request
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACRDREQ DMACRDREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMARDADR DMARDCLR DMARDREQ

DMARDADR : DMARDADR
bits : 2 - 7 (6 bit)
access : read-write

DMARDCLR : DMARDCLR
bits : 30 - 30 (1 bit)
access : read-write

DMARDREQ : DMARDREQ
bits : 31 - 31 (1 bit)
access : read-write


DMACRDVL

DMAC Read Value
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACRDVL DMACRDVL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMARDDATA

DMARDDATA : DMARDDATA
bits : 0 - 31 (32 bit)
access : read-only


UDC2RDREQ

UDC2 Read Request
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDC2RDREQ UDC2RDREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDC2RDADR UDC2RDCLR UDC2RDREQ

UDC2RDADR : UDC2RDADR
bits : 2 - 9 (8 bit)
access : read-write

UDC2RDCLR : UDC2RDCLR
bits : 30 - 30 (1 bit)
access : read-write

UDC2RDREQ : UDC2RDREQ
bits : 31 - 31 (1 bit)
access : read-write


UDC2RDVL

UDC2 Read Value
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UDC2RDVL UDC2RDVL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDC2RDATA

UDC2RDATA : UDC2RDATA
bits : 0 - 15 (16 bit)
access : read-only


ARBTSET

Arbiter Setting
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARBTSET ARBTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABTPRI_R0 ABTPRI_R1 ABTPRI_W0 ABTPRI_W1 ABTMOD ABT_EN

ABTPRI_R0 : ABTPRI_R0
bits : 0 - 1 (2 bit)
access : read-write

ABTPRI_R1 : ABTPRI_R1
bits : 4 - 5 (2 bit)
access : read-only

ABTPRI_W0 : ABTPRI_W0
bits : 8 - 9 (2 bit)
access : read-write

ABTPRI_W1 : ABTPRI_W1
bits : 12 - 13 (2 bit)
access : read-write

ABTMOD : ABTMOD
bits : 28 - 28 (1 bit)
access : read-write

ABT_EN : ABT_EN
bits : 31 - 31 (1 bit)
access : read-write


INTENB

Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENB INTENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPEND_RESUME_EN RESET_EN RESET_END_EN MW_SET_ADD_EN MW_END_ADD_EN MW_TIMEOUT_EN MW_AHBERR_EN MR_END_ADD_EN MR_EP_DSET_EN MR_AHBERR_EN UDC2_REG_RD_EN DMAC_REG_RD_EN POWER_DETECT_EN MW_RERROR_EN

SUSPEND_RESUME_EN : SUSPEND_RESUME_EN
bits : 8 - 8 (1 bit)
access : read-write

RESET_EN : RESET_EN
bits : 9 - 9 (1 bit)
access : read-write

RESET_END_EN : RESET_END_EN
bits : 10 - 10 (1 bit)
access : read-write

MW_SET_ADD_EN : MW_SET_ADD_EN
bits : 17 - 17 (1 bit)
access : read-write

MW_END_ADD_EN : MW_END_ADD_EN
bits : 18 - 18 (1 bit)
access : read-write

MW_TIMEOUT_EN : MW_TIMEOUT_EN
bits : 19 - 19 (1 bit)
access : read-write

MW_AHBERR_EN : MW_AHBERR_EN
bits : 20 - 20 (1 bit)
access : read-write

MR_END_ADD_EN : MR_END_ADD_EN
bits : 21 - 21 (1 bit)
access : read-write

MR_EP_DSET_EN : MR_EP_DSET_EN
bits : 22 - 22 (1 bit)
access : read-write

MR_AHBERR_EN : MR_AHBERR_EN
bits : 23 - 23 (1 bit)
access : read-write

UDC2_REG_RD_EN : UDC2_REG_RD_EN
bits : 24 - 24 (1 bit)
access : read-write

DMAC_REG_RD_EN : DMAC_REG_RD_EN
bits : 25 - 25 (1 bit)
access : read-write

POWER_DETECT_EN : POWER_DETECT_EN
bits : 28 - 28 (1 bit)
access : read-write

MW_RERROR_EN : MW_RERROR_EN
bits : 29 - 29 (1 bit)
access : read-write


MWSADR

Master Write Start Address
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MWSADR MWSADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MWSADR

MWSADR : MWSADR
bits : 0 - 31 (32 bit)
access : read-write


MWEADR

Master Write End Address
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MWEADR MWEADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MWEADR

MWEADR : MWEADR
bits : 0 - 31 (32 bit)
access : read-write


MWCADR

Master Write Current Address
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MWCADR MWCADR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MWCADR

MWCADR : MWCADR
bits : 0 - 31 (32 bit)
access : read-only


MWAHBADR

Master Write AHB Address
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MWAHBADR MWAHBADR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MWAHBADR

MWAHBADR : MWAHBADR
bits : 0 - 31 (32 bit)
access : read-only


MRSADR

Master Read Start Address
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRSADR MRSADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MRSADR

MRSADR : MRSADR
bits : 0 - 31 (32 bit)
access : read-write


MREADR

Master Read End Address
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MREADR MREADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MREADR

MREADR : MREADR
bits : 0 - 31 (32 bit)
access : read-write


MRCADR

Master Read Current Address
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MRCADR MRCADR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MRCADR

MRCADR : MRCADR
bits : 0 - 31 (32 bit)
access : read-only


MRAHBADR

Master Read AHB Address
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MRAHBADR MRAHBADR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MRAHBADR

MRAHBADR : MRAHBADR
bits : 0 - 31 (32 bit)
access : read-only


MWTOUT

Master Write Timeout Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MWTOUT MWTOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUT_EN TIMEOUTSET

TIMEOUT_EN : TIMEOUT_EN
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUTSET : TIMEOUTSET
bits : 1 - 31 (31 bit)
access : read-write


PWCTL

Power Detect Control
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWCTL PWCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RESET PW_RESETB PW_DETECT PHY_SUSPEND SUSPEND_X PHY_RESETB PHY_REMOTE_WKUP WAKEUP_EN

USB_RESET : USB_RESET
bits : 0 - 0 (1 bit)
access : read-only

PW_RESETB : PW_RESETB
bits : 1 - 1 (1 bit)
access : read-write

PW_DETECT : PW_DETECT
bits : 2 - 2 (1 bit)
access : read-only

PHY_SUSPEND : PHY_SUSPEND
bits : 3 - 3 (1 bit)
access : read-write

SUSPEND_X : SUSPEND_X
bits : 4 - 4 (1 bit)
access : read-only

PHY_RESETB : PHY_RESETB
bits : 5 - 5 (1 bit)
access : read-write

PHY_REMOTE_WKUP : PHY_REMOTE_WKUP
bits : 6 - 6 (1 bit)
access : read-write

WAKEUP_EN : WAKEUP_EN
bits : 7 - 7 (1 bit)
access : read-write


MSTSTS

Master Status
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSTSTS MSTSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MWEPDSET MREPDSET MWBFEMP MRBFEMP MREPEMPTY

MWEPDSET : MWEPDSET
bits : 0 - 0 (1 bit)
access : read-only

MREPDSET : MREPDSET
bits : 1 - 1 (1 bit)
access : read-only

MWBFEMP : MWBFEMP
bits : 2 - 2 (1 bit)
access : read-only

MRBFEMP : MRBFEMP
bits : 3 - 3 (1 bit)
access : read-only

MREPEMPTY : MREPEMPTY
bits : 4 - 4 (1 bit)
access : read-only


TOUTCNT

Timeout Count
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TOUTCNT TOUTCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMOUTCNT

TMOUTCNT : TMOUTCNT
bits : 0 - 31 (32 bit)
access : read-only


C2STSET

UDC2 setting
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2STSET C2STSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX0 EOPB_ENABLE

TX0 : TX0
bits : 0 - 0 (1 bit)
access : read-write

EOPB_ENABLE : EOPB_ENABLE
bits : 4 - 4 (1 bit)
access : read-write



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