\n

ADILV

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

Registers

MO1

MO2

MO3


MO1

Dual Unit Mode Trigger Controller START Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MO1 MO1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWATRG

SWATRG : SWATRG
bits : 7 - 7 (1 bit)
access : write-only


MO2

Dual Unit Mode Trigger Controller START Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MO2 MO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGAEN TRGASEL TRGASTA ADILV

TRGAEN : TRGAEN
bits : 0 - 0 (1 bit)
access : read-write

TRGASEL : TRGASEL
bits : 1 - 3 (3 bit)
access : read-write

TRGASTA : TRGASTA
bits : 4 - 4 (1 bit)
access : read-only

ADILV : ADILV
bits : 7 - 7 (1 bit)
access : read-write


MO3

Dual Unit Mode Trigger Controller START Register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MO3 MO3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORCNT

CORCNT : CORCNT
bits : 0 - 7 (8 bit)
access : read-write



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