\n

DA0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CNT

VCTL

REG

DCTL

TCTL


CNT

DAC Control Register1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OP REFON

OP : OP
bits : 0 - 0 (1 bit)
access : read-write

REFON : REFON
bits : 1 - 1 (1 bit)
access : read-write


VCTL

DAC Control Register2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCTL VCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHOLDCTF VHOLDCTB

VHOLDCTF : VHOLDCTF
bits : 0 - 3 (4 bit)
access : read-write

VHOLDCTB : VHOLDCTB
bits : 4 - 7 (4 bit)
access : read-write


REG

DAC Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REG REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC

DAC : DAC
bits : 6 - 15 (10 bit)
access : read-write


DCTL

DAC Output Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCTL DCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVE DMAEN TRGEN TRGSEL AMPSEL OFFSET

WAVE : WAVE
bits : 0 - 1 (2 bit)
access : read-write

DMAEN : DMAEN
bits : 7 - 7 (1 bit)
access : read-write

TRGEN : TRGEN
bits : 8 - 8 (1 bit)
access : read-write

TRGSEL : TRGSEL
bits : 9 - 11 (3 bit)
access : read-write

AMPSEL : AMPSEL
bits : 16 - 17 (2 bit)
access : read-write

OFFSET : OFFSET
bits : 18 - 20 (3 bit)
access : read-write


TCTL

DAC Trigger Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TCTL TCTL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRG DACCLR

SWTRG : SWTRG
bits : 0 - 0 (1 bit)
access : write-only

DACCLR : DACCLR
bits : 15 - 15 (1 bit)
access : write-only



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