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CG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

SYSCR

PCKSTP

PROTECT

OSCCR

IMCGA

IMCGB

IMCGC

IMCGD

ICRCG

RSTFLG

NMIFLG

STBYCR

PLLSEL


SYSCR

System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCR SYSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEAR PRCK FPSEL SCOSEL FCSTOP

GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write

PRCK : PRCK
bits : 8 - 10 (3 bit)
access : read-write

FPSEL : FPSEL
bits : 12 - 12 (1 bit)
access : read-write

SCOSEL : SCOSEL
bits : 16 - 17 (2 bit)
access : read-write

FCSTOP : FCSTOP
bits : 20 - 20 (1 bit)
access : read-write


PCKSTP

Peripheral Clock Stop Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCKSTP PCKSTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBDSTP USBHSTP CANSTP EMSTP

USBDSTP : USBDSTP
bits : 0 - 0 (1 bit)
access : read-write

USBHSTP : USBHSTP
bits : 1 - 1 (1 bit)
access : read-write

CANSTP : CANSTP
bits : 2 - 2 (1 bit)
access : read-write

EMSTP : EMSTP
bits : 3 - 3 (1 bit)
access : read-write


PROTECT

Protect Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROTECT PROTECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGPROTECT

CGPROTECT : CGPROTECT
bits : 0 - 7 (8 bit)
access : read-write


OSCCR

Oscillation Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCCR OSCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUEON WUEF PLLON WUPSEL1 XEN1 XTEN XEN3 DRVOSCH DRVOSCL WUPTL XEN2 OSCSEL EHOSCSEL WUPSEL2 WUPT

WUEON : WUEON
bits : 0 - 0 (1 bit)
access : write-only

WUEF : WUEF
bits : 1 - 1 (1 bit)
access : read-only

PLLON : PLLON
bits : 2 - 2 (1 bit)
access : read-write

WUPSEL1 : WUPSEL1
bits : 3 - 3 (1 bit)
access : read-write

XEN1 : XEN1
bits : 8 - 8 (1 bit)
access : read-write

XTEN : XTEN
bits : 9 - 9 (1 bit)
access : read-write

XEN3 : XEN3
bits : 10 - 10 (1 bit)
access : read-write

DRVOSCH : DRVOSCH
bits : 12 - 12 (1 bit)
access : read-write

DRVOSCL : DRVOSCL
bits : 13 - 13 (1 bit)
access : read-write

WUPTL : WUPTL
bits : 14 - 15 (2 bit)
access : read-write

XEN2 : XEN2
bits : 16 - 16 (1 bit)
access : read-write

OSCSEL : OSCSEL
bits : 17 - 17 (1 bit)
access : read-write

EHOSCSEL : EHOSCSEL
bits : 18 - 18 (1 bit)
access : read-write

WUPSEL2 : WUPSEL2
bits : 19 - 19 (1 bit)
access : read-write

WUPT : WUPT
bits : 20 - 31 (12 bit)
access : read-write


IMCGA

CG Interrupt Mode Control Register A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGA IMCGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT0EN EMST0 EMCG0 INT1EN EMST1 EMCG1 INT2EN EMST2 EMCG2 INT3EN EMST3 EMCG3

INT0EN : INT0EN
bits : 0 - 0 (1 bit)
access : read-write

EMST0 : EMST0
bits : 2 - 3 (2 bit)
access : read-only

EMCG0 : EMCG0
bits : 4 - 6 (3 bit)
access : read-write

INT1EN : INT1EN
bits : 8 - 8 (1 bit)
access : read-write

EMST1 : EMST1
bits : 10 - 11 (2 bit)
access : read-only

EMCG1 : EMCG1
bits : 12 - 14 (3 bit)
access : read-write

INT2EN : INT2EN
bits : 16 - 16 (1 bit)
access : read-write

EMST2 : EMST2
bits : 18 - 19 (2 bit)
access : read-only

EMCG2 : EMCG2
bits : 20 - 22 (3 bit)
access : read-write

INT3EN : INT3EN
bits : 24 - 24 (1 bit)
access : read-write

EMST3 : EMST3
bits : 26 - 27 (2 bit)
access : read-only

EMCG3 : EMCG3
bits : 28 - 30 (3 bit)
access : read-write


IMCGB

CG Interrupt Mode Control Register B
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGB IMCGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT4EN EMST4 EMCG4 INT5EN EMST5 EMCG5 INT6EN EMST6 EMCG6 INT7EN EMST7 EMCG7

INT4EN : INT4EN
bits : 0 - 0 (1 bit)
access : read-write

EMST4 : EMST4
bits : 2 - 3 (2 bit)
access : read-only

EMCG4 : EMCG4
bits : 4 - 6 (3 bit)
access : read-write

INT5EN : INT5EN
bits : 8 - 8 (1 bit)
access : read-write

EMST5 : EMST5
bits : 10 - 11 (2 bit)
access : read-only

EMCG5 : EMCG5
bits : 12 - 14 (3 bit)
access : read-write

INT6EN : INT6EN
bits : 16 - 16 (1 bit)
access : read-write

EMST6 : EMST6
bits : 18 - 19 (2 bit)
access : read-only

EMCG6 : EMCG6
bits : 20 - 22 (3 bit)
access : read-write

INT7EN : INT7EN
bits : 24 - 24 (1 bit)
access : read-write

EMST7 : EMST7
bits : 26 - 27 (2 bit)
access : read-only

EMCG7 : EMCG7
bits : 28 - 30 (3 bit)
access : read-write


IMCGC

CG Interrupt Mode Control Register C
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGC IMCGC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT8EN EMST8 EMCG8 INT9EN EMST9 EMCG9 INTAEN EMSTA EMCGA INTBEN EMSTB EMCGB

INT8EN : INT8EN
bits : 0 - 0 (1 bit)
access : read-write

EMST8 : EMST8
bits : 2 - 3 (2 bit)
access : read-only

EMCG8 : EMCG8
bits : 4 - 6 (3 bit)
access : read-write

INT9EN : INT9EN
bits : 8 - 8 (1 bit)
access : read-write

EMST9 : EMST9
bits : 10 - 11 (2 bit)
access : read-only

EMCG9 : EMCG9
bits : 12 - 14 (3 bit)
access : read-write

INTAEN : INTAEN
bits : 16 - 16 (1 bit)
access : read-write

EMSTA : EMSTA
bits : 18 - 19 (2 bit)
access : read-only

EMCGA : EMCGA
bits : 20 - 22 (3 bit)
access : read-write

INTBEN : INTBEN
bits : 24 - 24 (1 bit)
access : read-write

EMSTB : EMSTB
bits : 26 - 27 (2 bit)
access : read-only

EMCGB : EMCGB
bits : 28 - 30 (3 bit)
access : read-write


IMCGD

CG Interrupt Mode Control Register D
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGD IMCGD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTUSBWKUPEN EMSTUSBWKUP EMCGUSBWKUP INTDEN EMSTD EMCGD INTRTCEN EMSTRTC EMCGRTC INTRMCRXEN EMSTRMCRX EMCGRMCRX

INTUSBWKUPEN : INTUSBWKUPEN
bits : 0 - 0 (1 bit)
access : read-write

EMSTUSBWKUP : EMSTUSBWKUP
bits : 2 - 3 (2 bit)
access : read-only

EMCGUSBWKUP : EMCGUSBWKUP
bits : 4 - 6 (3 bit)
access : read-write

INTDEN : INTDEN
bits : 8 - 8 (1 bit)
access : read-write

EMSTD : EMSTD
bits : 10 - 11 (2 bit)
access : read-only

EMCGD : EMCGD
bits : 12 - 14 (3 bit)
access : read-write

INTRTCEN : INTRTCEN
bits : 16 - 16 (1 bit)
access : read-write

EMSTRTC : EMSTRTC
bits : 18 - 19 (2 bit)
access : read-only

EMCGRTC : EMCGRTC
bits : 20 - 22 (3 bit)
access : read-write

INTRMCRXEN : INTRMCRXEN
bits : 24 - 24 (1 bit)
access : read-write

EMSTRMCRX : EMSTRMCRX
bits : 26 - 27 (2 bit)
access : read-only

EMCGRMCRX : EMCGRMCRX
bits : 28 - 30 (3 bit)
access : read-write


ICRCG

CG Interrupt Request Clear Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICRCG ICRCG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICRCG

ICRCG : ICRCG
bits : 0 - 4 (5 bit)
access : write-only


RSTFLG

Reset Flag Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTFLG RSTFLG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PONRSTF PINRSTF WDTRSTF STOP2RSTF DBGRSTF OFDRSTF LVDRSTF

PONRSTF : PONRSTF
bits : 0 - 0 (1 bit)
access : read-write

PINRSTF : PINRSTF
bits : 1 - 1 (1 bit)
access : read-write

WDTRSTF : WDTRSTF
bits : 2 - 2 (1 bit)
access : read-write

STOP2RSTF : STOP2RSTF
bits : 3 - 3 (1 bit)
access : read-write

DBGRSTF : DBGRSTF
bits : 4 - 4 (1 bit)
access : read-write

OFDRSTF : OFDRSTF
bits : 5 - 5 (1 bit)
access : read-write

LVDRSTF : LVDRSTF
bits : 6 - 6 (1 bit)
access : read-write


NMIFLG

NMI Flag Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NMIFLG NMIFLG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIFLG0 NMIFLG1 NMIFLG2 NMIFLG3

NMIFLG0 : NMIFLG0
bits : 0 - 0 (1 bit)
access : read-only

NMIFLG1 : NMIFLG1
bits : 1 - 1 (1 bit)
access : read-only

NMIFLG2 : NMIFLG2
bits : 2 - 2 (1 bit)
access : read-only

NMIFLG3 : NMIFLG3
bits : 3 - 3 (1 bit)
access : read-only


STBYCR

Standby Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STBYCR STBYCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STBY DRVE PTKEEP

STBY : STBY
bits : 0 - 2 (3 bit)
access : read-write

DRVE : DRVE
bits : 16 - 16 (1 bit)
access : read-write

PTKEEP : PTKEEP
bits : 17 - 17 (1 bit)
access : read-write


PLLSEL

PLL Selection Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLSEL PLLSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLSEL PLLSET

PLLSEL : PLLSEL
bits : 0 - 0 (1 bit)
access : read-write

PLLSET : PLLSET
bits : 1 - 15 (15 bit)
access : read-write



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