\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
DAC Control Register1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OP : OP
bits : 0 - 0 (1 bit)
access : read-write
REFON : REFON
bits : 1 - 1 (1 bit)
access : read-write
DAC Control Register2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VHOLDCTF : VHOLDCTF
bits : 0 - 3 (4 bit)
access : read-write
VHOLDCTB : VHOLDCTB
bits : 4 - 7 (4 bit)
access : read-write
DAC Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAC : DAC
bits : 6 - 15 (10 bit)
access : read-write
DAC Output Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAVE : WAVE
bits : 0 - 1 (2 bit)
access : read-write
DMAEN : DMAEN
bits : 7 - 7 (1 bit)
access : read-write
TRGEN : TRGEN
bits : 8 - 8 (1 bit)
access : read-write
TRGSEL : TRGSEL
bits : 9 - 11 (3 bit)
access : read-write
AMPSEL : AMPSEL
bits : 16 - 17 (2 bit)
access : read-write
OFFSET : OFFSET
bits : 18 - 20 (3 bit)
access : read-write
DAC Trigger Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWTRG : SWTRG
bits : 0 - 0 (1 bit)
access : write-only
DACCLR : DACCLR
bits : 15 - 15 (1 bit)
access : write-only
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