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EM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0xFE8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1000 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1004 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1008 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1010 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1014 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1018 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x101C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1020 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1024 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1028 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x102C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1030 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1034 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1038 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x103C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1040 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1044 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1048 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x104C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1050 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1054 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1058 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x105C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1060 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x106C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1070 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1074 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1078 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1080 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x10C8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10D0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x10D4 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10DC Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1104 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1108 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x110C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1110 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1114 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1118 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x111C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1120 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1124 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1128 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x112C Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1150 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x115C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1160 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1170 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x11C0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x11C4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x11C8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x11CC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x11D0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x11E0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x11E4 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IFVRR

IFINTST

DCR

DTEN

DREN

DTDPR

DRDPR

DINTST

DINTEN

DERR

DMFCR

DTFTR

DFCDR

DRRCR

DEADR

DTUFR

DROFR

DRBTR

DRPDR

DTIMER

DRBAR

DRDAR

DTBAR

DTDAR

CCR

CRFLR

CINTST

CINTEN

CMIICR

CPHYST

CICR

CAPR

CMPR

CRPCR

CPULR

CPCR

CBRR

CMAHR

CMALR

CTRER

CTCDR

CTCLR

CTNDR

CRCER

CRFER

CRLSR

CRLOR

CRRFR

CRMFR

IFINTEN

IFCR


IFVRR

ADiC Version_Revision Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IFVRR IFVRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REV VER

REV : REV
bits : 0 - 15 (16 bit)
access : read-only

VER : VER
bits : 16 - 31 (16 bit)
access : read-only


IFINTST

ADiC Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFINTST IFINTST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EMDMACINT SLAVE0 SLAVE1 SLAVE2 SLAVE3 IOTOUT MASTER0 MASTER1 MASTER2 DMATOUT

EMDMACINT : EMDMACINT
bits : 0 - 0 (1 bit)
access : read-write

SLAVE0 : SLAVE0
bits : 8 - 8 (1 bit)
access : read-write

SLAVE1 : SLAVE1
bits : 9 - 9 (1 bit)
access : read-write

SLAVE2 : SLAVE2
bits : 10 - 10 (1 bit)
access : read-write

SLAVE3 : SLAVE3
bits : 11 - 11 (1 bit)
access : read-write

IOTOUT : IOTOUT
bits : 15 - 15 (1 bit)
access : read-write

MASTER0 : MASTER0
bits : 16 - 16 (1 bit)
access : read-write

MASTER1 : MASTER1
bits : 17 - 17 (1 bit)
access : read-write

MASTER2 : MASTER2
bits : 18 - 18 (1 bit)
access : read-write

DMATOUT : DMATOUT
bits : 23 - 23 (1 bit)
access : read-write


DCR

EMDMAC Movement Control Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCR DCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWR DL DE

SWR : SWR
bits : 0 - 0 (1 bit)
access : read-write

DL : DL
bits : 4 - 5 (2 bit)
access : read-write

DE : DE
bits : 6 - 6 (1 bit)
access : read-write


DTEN

Transmission Instructions Register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTEN DTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRNS

TRNS : TRNS
bits : 0 - 0 (1 bit)
access : read-write


DREN

Reception instructions Register
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DREN DREN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCV

RCV : RCV
bits : 0 - 0 (1 bit)
access : read-write


DTDPR

Transmission Dscripter top address setting Register
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTDPR DTDPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDPA

TDPA : TDPA
bits : 0 - 31 (32 bit)
access : read-write


DRDPR

Reception Dscripter top address setting Register
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRDPR DRDPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDPA

RDPA : RDPA
bits : 0 - 31 (32 bit)
access : read-write


DINTST

EMSMAC Interrupt Status Indication Register
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DINTST DINTST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RINT1 RINT2 RINT3 RINT4 RINT5 RINT8 TINT1 TINT2 TINT3 TINT4 RFE RDE FRC TFE TDE FTC MINT BER RFRMER RABT TABT TWB

RINT1 : RINT1
bits : 0 - 0 (1 bit)
access : read-write

RINT2 : RINT2
bits : 1 - 1 (1 bit)
access : read-write

RINT3 : RINT3
bits : 2 - 2 (1 bit)
access : read-write

RINT4 : RINT4
bits : 3 - 3 (1 bit)
access : read-write

RINT5 : RINT5
bits : 4 - 4 (1 bit)
access : read-write

RINT8 : RINT8
bits : 7 - 7 (1 bit)
access : read-write

TINT1 : TINT1
bits : 8 - 8 (1 bit)
access : read-write

TINT2 : TINT2
bits : 9 - 9 (1 bit)
access : read-write

TINT3 : TINT3
bits : 10 - 10 (1 bit)
access : read-write

TINT4 : TINT4
bits : 11 - 11 (1 bit)
access : read-write

RFE : RFE
bits : 16 - 16 (1 bit)
access : read-write

RDE : RDE
bits : 17 - 17 (1 bit)
access : read-write

FRC : FRC
bits : 18 - 18 (1 bit)
access : read-write

TFE : TFE
bits : 19 - 19 (1 bit)
access : read-write

TDE : TDE
bits : 20 - 20 (1 bit)
access : read-write

FTC : FTC
bits : 21 - 21 (1 bit)
access : read-write

MINT : MINT
bits : 22 - 22 (1 bit)
access : read-write

BER : BER
bits : 23 - 23 (1 bit)
access : read-write

RFRMER : RFRMER
bits : 24 - 24 (1 bit)
access : read-write

RABT : RABT
bits : 25 - 25 (1 bit)
access : read-write

TABT : TABT
bits : 26 - 26 (1 bit)
access : read-write

TWB : TWB
bits : 30 - 30 (1 bit)
access : read-write


DINTEN

EMDMAC Interrupt mask setting Register
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DINTEN DINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RINT1 RINT2 RINT3 RINT4 RINT5 RINT8 TINT1 TINT2 TINT3 TINT4 RFE RDE FRC TFE TDE FTC MINT BER RFRMER RABT TABT TWB

RINT1 : RINT1
bits : 0 - 0 (1 bit)
access : read-write

RINT2 : RINT2
bits : 1 - 1 (1 bit)
access : read-write

RINT3 : RINT3
bits : 2 - 2 (1 bit)
access : read-write

RINT4 : RINT4
bits : 3 - 3 (1 bit)
access : read-write

RINT5 : RINT5
bits : 4 - 4 (1 bit)
access : read-write

RINT8 : RINT8
bits : 7 - 7 (1 bit)
access : read-write

TINT1 : TINT1
bits : 8 - 8 (1 bit)
access : read-write

TINT2 : TINT2
bits : 9 - 9 (1 bit)
access : read-write

TINT3 : TINT3
bits : 10 - 10 (1 bit)
access : read-write

TINT4 : TINT4
bits : 11 - 11 (1 bit)
access : read-write

RFE : RFE
bits : 16 - 16 (1 bit)
access : read-write

RDE : RDE
bits : 17 - 17 (1 bit)
access : read-write

FRC : FRC
bits : 18 - 18 (1 bit)
access : read-write

TFE : TFE
bits : 19 - 19 (1 bit)
access : read-write

TDE : TDE
bits : 20 - 20 (1 bit)
access : read-write

FTC : FTC
bits : 21 - 21 (1 bit)
access : read-write

MINT : MINT
bits : 22 - 22 (1 bit)
access : read-write

BER : BER
bits : 23 - 23 (1 bit)
access : read-write

RFRMER : RFRMER
bits : 24 - 24 (1 bit)
access : read-write

RABT : RABT
bits : 25 - 25 (1 bit)
access : read-write

TABT : TABT
bits : 26 - 26 (1 bit)
access : read-write

TWB : TWB
bits : 30 - 30 (1 bit)
access : read-write


DERR

Err Mask Setting Register
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DERR DERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RINT1 RINT2 RINT3 RINT4 RINT5 RINT8 TINT1 TINT2 TINT3 TINT4

RINT1 : RINT1
bits : 0 - 0 (1 bit)
access : read-write

RINT2 : RINT2
bits : 1 - 1 (1 bit)
access : read-write

RINT3 : RINT3
bits : 2 - 2 (1 bit)
access : read-write

RINT4 : RINT4
bits : 3 - 3 (1 bit)
access : read-write

RINT5 : RINT5
bits : 4 - 4 (1 bit)
access : read-write

RINT8 : RINT8
bits : 7 - 7 (1 bit)
access : read-write

TINT1 : TINT1
bits : 8 - 8 (1 bit)
access : read-write

TINT2 : TINT2
bits : 9 - 9 (1 bit)
access : read-write

TINT3 : TINT3
bits : 10 - 10 (1 bit)
access : read-write

TINT4 : TINT4
bits : 11 - 11 (1 bit)
access : read-write


DMFCR

Disposal Frame Count Register
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMFCR DMFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIS

MIS : MIS
bits : 0 - 15 (16 bit)
access : read-write


DTFTR

Transmission FIFO thresholding Register
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTFTR DTFTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFTH

TFTH : TFTH
bits : 0 - 10 (11 bit)
access : read-write


DFCDR

Outside FIFO Capacity Setting Register
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFCDR DFCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RA TA

RA : RA
bits : 0 - 4 (5 bit)
access : read-write

TA : TA
bits : 8 - 12 (5 bit)
access : read-write


DRRCR

Reception Start Reset Setting Register
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRRCR DRRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RR RNR

RR : RR
bits : 0 - 0 (1 bit)
access : read-write

RNR : RNR
bits : 1 - 1 (1 bit)
access : read-write


DEADR

DMA Error Address Register
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEADR DEADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADR

ERRADR : ERRADR
bits : 0 - 31 (32 bit)
access : read-write


DTUFR

Transmission FIFO Underflow Count Register
address_offset : 0x1064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTUFR DTUFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UNDER

UNDER : UNDER
bits : 0 - 15 (16 bit)
access : read-write


DROFR

Reception FIFO Underflow Count Register
address_offset : 0x1068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DROFR DROFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVER

OVER : OVER
bits : 0 - 15 (16 bit)
access : read-write


DRBTR

Transmission FIFO Busy Transmission Thresholding Register
address_offset : 0x1070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRBTR DRBTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFDO RFFO

RFDO : RFDO
bits : 0 - 2 (3 bit)
access : read-write

RFFO : RFFO
bits : 16 - 18 (3 bit)
access : read-write


DRPDR

Reception Data Padding setting Register
address_offset : 0x1078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRPDR DRPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADR PADS

PADR : PADR
bits : 0 - 5 (6 bit)
access : read-write

PADS : PADS
bits : 16 - 17 (2 bit)
access : read-write


DTIMER

Transmission Interrupt Mode Setting Register
address_offset : 0x107C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTIMER DTIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIS TIM

TIS : TIS
bits : 0 - 0 (1 bit)
access : read-write

TIM : TIM
bits : 4 - 4 (1 bit)
access : read-write


DRBAR

Reception Buffer Light Address For debugging Register
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DRBAR DRBAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBWA

RBWA : RBWA
bits : 0 - 31 (32 bit)
access : read-only


DRDAR

Reception Dscripter Read Address For Debugging Register
address_offset : 0x10CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DRDAR DRDAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRA

RDRA : RDRA
bits : 0 - 31 (32 bit)
access : read-only


DTBAR

Transmission Read Address For Debugging Register
address_offset : 0x10D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTBAR DTBAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBRA

TBRA : TBRA
bits : 0 - 31 (32 bit)
access : read-only


DTDAR

Transmission Dscripter Read Address For Debugging Register
address_offset : 0x10D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTDAR DTDAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDRA

TDRA : TDRA
bits : 0 - 31 (32 bit)
access : read-only


CCR

Ether FeLic Active Mode Register
address_offset : 0x1100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRM DPM OLB ILB TPE RPE MPM CER TXF RXF PFR TPF TPC

PRM : PRM
bits : 0 - 0 (1 bit)
access : read-write

DPM : DPM
bits : 1 - 1 (1 bit)
access : read-write

OLB : OLB
bits : 2 - 2 (1 bit)
access : read-write

ILB : ILB
bits : 3 - 3 (1 bit)
access : read-write

TPE : TPE
bits : 5 - 5 (1 bit)
access : read-write

RPE : RPE
bits : 6 - 6 (1 bit)
access : read-write

MPM : MPM
bits : 9 - 9 (1 bit)
access : read-write

CER : CER
bits : 12 - 12 (1 bit)
access : read-write

TXF : TXF
bits : 16 - 16 (1 bit)
access : read-write

RXF : RXF
bits : 17 - 17 (1 bit)
access : read-write

PFR : PFR
bits : 18 - 18 (1 bit)
access : read-write

TPF : TPF
bits : 19 - 19 (1 bit)
access : read-write

TPC : TPC
bits : 20 - 20 (1 bit)
access : read-write


CRFLR

Long Frame Length Check Level Setting Register
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRFLR CRFLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLEN_ULMT

FLEN_ULMT : FLEN_ULMT
bits : 0 - 11 (12 bit)
access : read-write


CINTST

Status indication Register
address_offset : 0x1110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CINTST CINTST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCIDTCT MAGICPKT LINKCHNG PSRTROV BRDSRCV

FCIDTCT : FCIDTCT
bits : 0 - 0 (1 bit)
access : read-write

MAGICPKT : MAGICPKT
bits : 1 - 1 (1 bit)
access : read-write

LINKCHNG : LINKCHNG
bits : 2 - 2 (1 bit)
access : read-write

PSRTROV : PSRTROV
bits : 4 - 4 (1 bit)
access : read-write

BRDSRCV : BRDSRCV
bits : 5 - 5 (1 bit)
access : read-write


CINTEN

Interrupt mask setting Register
address_offset : 0x1118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CINTEN CINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCIDTCT MAGICPKT LINKCHNG PSRTROV BRDSRCV

FCIDTCT : FCIDTCT
bits : 0 - 0 (1 bit)
access : read-write

MAGICPKT : MAGICPKT
bits : 1 - 1 (1 bit)
access : read-write

LINKCHNG : LINKCHNG
bits : 2 - 2 (1 bit)
access : read-write

PSRTROV : PSRTROV
bits : 4 - 4 (1 bit)
access : read-write

BRDSRCV : BRDSRCV
bits : 5 - 5 (1 bit)
access : read-write


CMIICR

M Control Register
address_offset : 0x1120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMIICR CMIICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDC MMD MDO MDI

MDC : MDC
bits : 0 - 0 (1 bit)
access : read-write

MMD : MMD
bits : 1 - 1 (1 bit)
access : read-write

MDO : MDO
bits : 2 - 2 (1 bit)
access : read-write

MDI : MDI
bits : 3 - 3 (1 bit)
access : read-write


CPHYST

Status Signal Register
address_offset : 0x1128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPHYST CPHYST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINK

LINK : LINK
bits : 0 - 0 (1 bit)
access : read-only


CICR

IPG Counter Setting Register
address_offset : 0x1150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CICR CICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPG

IPG : IPG
bits : 0 - 4 (5 bit)
access : read-write


CAPR

Auto Pause Parameter Setting Register
address_offset : 0x1154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPR CAPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APAUSE

APAUSE : APAUSE
bits : 0 - 15 (16 bit)
access : read-write


CMPR

Manual Pause Parameter setting Register
address_offset : 0x1158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPR CMPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPAUSE

MPAUSE : MPAUSE
bits : 0 - 15 (16 bit)
access : write-only


CRPCR

Reception PAUSE Frame Counter Register
address_offset : 0x1160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CRPCR CRPCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPAUSE

RPAUSE : RPAUSE
bits : 0 - 7 (8 bit)
access : read-only


CPULR

PAUSE Frame Retransmission Number Of Times Setting Register
address_offset : 0x1164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPULR CPULR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPAUSE

TXPAUSE : TXPAUSE
bits : 0 - 15 (16 bit)
access : read-write


CPCR

PAUSE Frame Retransmission Number Of Times Counter Register
address_offset : 0x1168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPCR CPCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPAUSE

TPAUSE : TPAUSE
bits : 0 - 15 (16 bit)
access : read-only


CBRR

Broadcast Frame Reception Number Of Times Setting Register
address_offset : 0x116C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBRR CBRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCF

BCF : BCF
bits : 0 - 15 (16 bit)
access : read-write


CMAHR

Mac Address Register (High Rank)
address_offset : 0x11C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAHR CMAHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACADRH

MACADRH : MACADRH
bits : 0 - 31 (32 bit)
access : read-write


CMALR

Mac Address Register (Low Rank)
address_offset : 0x11C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMALR CMALR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACADRL

MACADRL : MACADRL
bits : 0 - 31 (32 bit)
access : read-write


CTRER

TINT1 Cunter Register
address_offset : 0x11D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRER CTRER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TINT1CNT

TINT1CNT : TINT1CNT
bits : 0 - 31 (32 bit)
access : read-write


CTCDR

TINT2 Cunter Register
address_offset : 0x11D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTCDR CTCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TINT2CNT

TINT2CNT : TINT2CNT
bits : 0 - 31 (32 bit)
access : read-write


CTCLR

TINT3 Cunter Register
address_offset : 0x11D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTCLR CTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TINT3CNT

TINT3CNT : TINT3CNT
bits : 0 - 31 (32 bit)
access : read-write


CTNDR

TINT4 Cunter Register
address_offset : 0x11DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTNDR CTNDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TINT4CNT

TINT4CNT : TINT4CNT
bits : 0 - 31 (32 bit)
access : read-write


CRCER

RINT1 Cunter Register
address_offset : 0x11E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCER CRCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RINT1CNT

RINT1CNT : RINT1CNT
bits : 0 - 31 (32 bit)
access : read-write


CRFER

RINT2 Cunter Register
address_offset : 0x11E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRFER CRFER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RINT2CNT

RINT2CNT : RINT2CNT
bits : 0 - 31 (32 bit)
access : read-write


CRLSR

RINT3 Cunter Register
address_offset : 0x11EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRLSR CRLSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RINT3CNT

RINT3CNT : RINT3CNT
bits : 0 - 31 (32 bit)
access : read-write


CRLOR

RINT4 Cunter Register
address_offset : 0x11F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRLOR CRLOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RINT4CNT

RINT4CNT : RINT4CNT
bits : 0 - 31 (32 bit)
access : read-write


CRRFR

RINT5 Cunter Register
address_offset : 0x11F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRRFR CRRFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RINT5CNT

RINT5CNT : RINT5CNT
bits : 0 - 31 (32 bit)
access : read-write


CRMFR

RINT8 Cunter Register
address_offset : 0x11F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRMFR CRMFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RINT8CNT

RINT8CNT : RINT8CNT
bits : 0 - 31 (32 bit)
access : read-write


IFINTEN

ADiC Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFINTEN IFINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EMDMACINT SLAVE0 SLAVE1 SLAVE2 SLAVE3 IOTOUT MASTER0 MASTER1 MASTER2 DMATOUT

EMDMACINT : EMDMACINT
bits : 0 - 0 (1 bit)
access : read-write

SLAVE0 : SLAVE0
bits : 8 - 8 (1 bit)
access : read-write

SLAVE1 : SLAVE1
bits : 9 - 9 (1 bit)
access : read-write

SLAVE2 : SLAVE2
bits : 10 - 10 (1 bit)
access : read-write

SLAVE3 : SLAVE3
bits : 11 - 11 (1 bit)
access : read-write

IOTOUT : IOTOUT
bits : 15 - 15 (1 bit)
access : read-write

MASTER0 : MASTER0
bits : 16 - 16 (1 bit)
access : read-write

MASTER1 : MASTER1
bits : 17 - 17 (1 bit)
access : read-write

MASTER2 : MASTER2
bits : 18 - 18 (1 bit)
access : read-write

DMATOUT : DMATOUT
bits : 23 - 23 (1 bit)
access : read-write


IFCR

ADiC MODE Setting Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR IFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOTOUT DMATOUT DMAERR

IOTOUT : IOTOUT
bits : 8 - 8 (1 bit)
access : read-write

DMATOUT : DMATOUT
bits : 9 - 9 (1 bit)
access : read-write

DMAERR : DMAERR
bits : 10 - 10 (1 bit)
access : read-write



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