\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0xFE8 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1000 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1004 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1008 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1010 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1014 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1018 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x101C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1020 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1024 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1028 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x102C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1030 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1034 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1038 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x103C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1040 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1044 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1048 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x104C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1050 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1054 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1058 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x105C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1060 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x106C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1070 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1074 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1078 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1080 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x10C8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10D0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x10D4 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10DC Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1104 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1108 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x110C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1110 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1114 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1118 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x111C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1120 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1124 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1128 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x112C Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1150 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x115C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1160 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1170 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x11C0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x11C4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x11C8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x11CC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x11D0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x11E0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x11E4 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
ADiC Version_Revision Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REV : REV
bits : 0 - 15 (16 bit)
access : read-only
VER : VER
bits : 16 - 31 (16 bit)
access : read-only
ADiC Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMDMACINT : EMDMACINT
bits : 0 - 0 (1 bit)
access : read-write
SLAVE0 : SLAVE0
bits : 8 - 8 (1 bit)
access : read-write
SLAVE1 : SLAVE1
bits : 9 - 9 (1 bit)
access : read-write
SLAVE2 : SLAVE2
bits : 10 - 10 (1 bit)
access : read-write
SLAVE3 : SLAVE3
bits : 11 - 11 (1 bit)
access : read-write
IOTOUT : IOTOUT
bits : 15 - 15 (1 bit)
access : read-write
MASTER0 : MASTER0
bits : 16 - 16 (1 bit)
access : read-write
MASTER1 : MASTER1
bits : 17 - 17 (1 bit)
access : read-write
MASTER2 : MASTER2
bits : 18 - 18 (1 bit)
access : read-write
DMATOUT : DMATOUT
bits : 23 - 23 (1 bit)
access : read-write
EMDMAC Movement Control Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWR : SWR
bits : 0 - 0 (1 bit)
access : read-write
DL : DL
bits : 4 - 5 (2 bit)
access : read-write
DE : DE
bits : 6 - 6 (1 bit)
access : read-write
Transmission Instructions Register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNS : TRNS
bits : 0 - 0 (1 bit)
access : read-write
Reception instructions Register
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCV : RCV
bits : 0 - 0 (1 bit)
access : read-write
Transmission Dscripter top address setting Register
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDPA : TDPA
bits : 0 - 31 (32 bit)
access : read-write
Reception Dscripter top address setting Register
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDPA : RDPA
bits : 0 - 31 (32 bit)
access : read-write
EMSMAC Interrupt Status Indication Register
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RINT1 : RINT1
bits : 0 - 0 (1 bit)
access : read-write
RINT2 : RINT2
bits : 1 - 1 (1 bit)
access : read-write
RINT3 : RINT3
bits : 2 - 2 (1 bit)
access : read-write
RINT4 : RINT4
bits : 3 - 3 (1 bit)
access : read-write
RINT5 : RINT5
bits : 4 - 4 (1 bit)
access : read-write
RINT8 : RINT8
bits : 7 - 7 (1 bit)
access : read-write
TINT1 : TINT1
bits : 8 - 8 (1 bit)
access : read-write
TINT2 : TINT2
bits : 9 - 9 (1 bit)
access : read-write
TINT3 : TINT3
bits : 10 - 10 (1 bit)
access : read-write
TINT4 : TINT4
bits : 11 - 11 (1 bit)
access : read-write
RFE : RFE
bits : 16 - 16 (1 bit)
access : read-write
RDE : RDE
bits : 17 - 17 (1 bit)
access : read-write
FRC : FRC
bits : 18 - 18 (1 bit)
access : read-write
TFE : TFE
bits : 19 - 19 (1 bit)
access : read-write
TDE : TDE
bits : 20 - 20 (1 bit)
access : read-write
FTC : FTC
bits : 21 - 21 (1 bit)
access : read-write
MINT : MINT
bits : 22 - 22 (1 bit)
access : read-write
BER : BER
bits : 23 - 23 (1 bit)
access : read-write
RFRMER : RFRMER
bits : 24 - 24 (1 bit)
access : read-write
RABT : RABT
bits : 25 - 25 (1 bit)
access : read-write
TABT : TABT
bits : 26 - 26 (1 bit)
access : read-write
TWB : TWB
bits : 30 - 30 (1 bit)
access : read-write
EMDMAC Interrupt mask setting Register
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RINT1 : RINT1
bits : 0 - 0 (1 bit)
access : read-write
RINT2 : RINT2
bits : 1 - 1 (1 bit)
access : read-write
RINT3 : RINT3
bits : 2 - 2 (1 bit)
access : read-write
RINT4 : RINT4
bits : 3 - 3 (1 bit)
access : read-write
RINT5 : RINT5
bits : 4 - 4 (1 bit)
access : read-write
RINT8 : RINT8
bits : 7 - 7 (1 bit)
access : read-write
TINT1 : TINT1
bits : 8 - 8 (1 bit)
access : read-write
TINT2 : TINT2
bits : 9 - 9 (1 bit)
access : read-write
TINT3 : TINT3
bits : 10 - 10 (1 bit)
access : read-write
TINT4 : TINT4
bits : 11 - 11 (1 bit)
access : read-write
RFE : RFE
bits : 16 - 16 (1 bit)
access : read-write
RDE : RDE
bits : 17 - 17 (1 bit)
access : read-write
FRC : FRC
bits : 18 - 18 (1 bit)
access : read-write
TFE : TFE
bits : 19 - 19 (1 bit)
access : read-write
TDE : TDE
bits : 20 - 20 (1 bit)
access : read-write
FTC : FTC
bits : 21 - 21 (1 bit)
access : read-write
MINT : MINT
bits : 22 - 22 (1 bit)
access : read-write
BER : BER
bits : 23 - 23 (1 bit)
access : read-write
RFRMER : RFRMER
bits : 24 - 24 (1 bit)
access : read-write
RABT : RABT
bits : 25 - 25 (1 bit)
access : read-write
TABT : TABT
bits : 26 - 26 (1 bit)
access : read-write
TWB : TWB
bits : 30 - 30 (1 bit)
access : read-write
Err Mask Setting Register
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RINT1 : RINT1
bits : 0 - 0 (1 bit)
access : read-write
RINT2 : RINT2
bits : 1 - 1 (1 bit)
access : read-write
RINT3 : RINT3
bits : 2 - 2 (1 bit)
access : read-write
RINT4 : RINT4
bits : 3 - 3 (1 bit)
access : read-write
RINT5 : RINT5
bits : 4 - 4 (1 bit)
access : read-write
RINT8 : RINT8
bits : 7 - 7 (1 bit)
access : read-write
TINT1 : TINT1
bits : 8 - 8 (1 bit)
access : read-write
TINT2 : TINT2
bits : 9 - 9 (1 bit)
access : read-write
TINT3 : TINT3
bits : 10 - 10 (1 bit)
access : read-write
TINT4 : TINT4
bits : 11 - 11 (1 bit)
access : read-write
Disposal Frame Count Register
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIS : MIS
bits : 0 - 15 (16 bit)
access : read-write
Transmission FIFO thresholding Register
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFTH : TFTH
bits : 0 - 10 (11 bit)
access : read-write
Outside FIFO Capacity Setting Register
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : RA
bits : 0 - 4 (5 bit)
access : read-write
TA : TA
bits : 8 - 12 (5 bit)
access : read-write
Reception Start Reset Setting Register
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RR : RR
bits : 0 - 0 (1 bit)
access : read-write
RNR : RNR
bits : 1 - 1 (1 bit)
access : read-write
DMA Error Address Register
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERRADR : ERRADR
bits : 0 - 31 (32 bit)
access : read-write
Transmission FIFO Underflow Count Register
address_offset : 0x1064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UNDER : UNDER
bits : 0 - 15 (16 bit)
access : read-write
Reception FIFO Underflow Count Register
address_offset : 0x1068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVER : OVER
bits : 0 - 15 (16 bit)
access : read-write
Transmission FIFO Busy Transmission Thresholding Register
address_offset : 0x1070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFDO : RFDO
bits : 0 - 2 (3 bit)
access : read-write
RFFO : RFFO
bits : 16 - 18 (3 bit)
access : read-write
Reception Data Padding setting Register
address_offset : 0x1078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADR : PADR
bits : 0 - 5 (6 bit)
access : read-write
PADS : PADS
bits : 16 - 17 (2 bit)
access : read-write
Transmission Interrupt Mode Setting Register
address_offset : 0x107C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIS : TIS
bits : 0 - 0 (1 bit)
access : read-write
TIM : TIM
bits : 4 - 4 (1 bit)
access : read-write
Reception Buffer Light Address For debugging Register
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RBWA : RBWA
bits : 0 - 31 (32 bit)
access : read-only
Reception Dscripter Read Address For Debugging Register
address_offset : 0x10CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDRA : RDRA
bits : 0 - 31 (32 bit)
access : read-only
Transmission Read Address For Debugging Register
address_offset : 0x10D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TBRA : TBRA
bits : 0 - 31 (32 bit)
access : read-only
Transmission Dscripter Read Address For Debugging Register
address_offset : 0x10D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TDRA : TDRA
bits : 0 - 31 (32 bit)
access : read-only
Ether FeLic Active Mode Register
address_offset : 0x1100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRM : PRM
bits : 0 - 0 (1 bit)
access : read-write
DPM : DPM
bits : 1 - 1 (1 bit)
access : read-write
OLB : OLB
bits : 2 - 2 (1 bit)
access : read-write
ILB : ILB
bits : 3 - 3 (1 bit)
access : read-write
TPE : TPE
bits : 5 - 5 (1 bit)
access : read-write
RPE : RPE
bits : 6 - 6 (1 bit)
access : read-write
MPM : MPM
bits : 9 - 9 (1 bit)
access : read-write
CER : CER
bits : 12 - 12 (1 bit)
access : read-write
TXF : TXF
bits : 16 - 16 (1 bit)
access : read-write
RXF : RXF
bits : 17 - 17 (1 bit)
access : read-write
PFR : PFR
bits : 18 - 18 (1 bit)
access : read-write
TPF : TPF
bits : 19 - 19 (1 bit)
access : read-write
TPC : TPC
bits : 20 - 20 (1 bit)
access : read-write
Long Frame Length Check Level Setting Register
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLEN_ULMT : FLEN_ULMT
bits : 0 - 11 (12 bit)
access : read-write
Status indication Register
address_offset : 0x1110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCIDTCT : FCIDTCT
bits : 0 - 0 (1 bit)
access : read-write
MAGICPKT : MAGICPKT
bits : 1 - 1 (1 bit)
access : read-write
LINKCHNG : LINKCHNG
bits : 2 - 2 (1 bit)
access : read-write
PSRTROV : PSRTROV
bits : 4 - 4 (1 bit)
access : read-write
BRDSRCV : BRDSRCV
bits : 5 - 5 (1 bit)
access : read-write
Interrupt mask setting Register
address_offset : 0x1118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCIDTCT : FCIDTCT
bits : 0 - 0 (1 bit)
access : read-write
MAGICPKT : MAGICPKT
bits : 1 - 1 (1 bit)
access : read-write
LINKCHNG : LINKCHNG
bits : 2 - 2 (1 bit)
access : read-write
PSRTROV : PSRTROV
bits : 4 - 4 (1 bit)
access : read-write
BRDSRCV : BRDSRCV
bits : 5 - 5 (1 bit)
access : read-write
M Control Register
address_offset : 0x1120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDC : MDC
bits : 0 - 0 (1 bit)
access : read-write
MMD : MMD
bits : 1 - 1 (1 bit)
access : read-write
MDO : MDO
bits : 2 - 2 (1 bit)
access : read-write
MDI : MDI
bits : 3 - 3 (1 bit)
access : read-write
Status Signal Register
address_offset : 0x1128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LINK : LINK
bits : 0 - 0 (1 bit)
access : read-only
IPG Counter Setting Register
address_offset : 0x1150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPG : IPG
bits : 0 - 4 (5 bit)
access : read-write
Auto Pause Parameter Setting Register
address_offset : 0x1154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APAUSE : APAUSE
bits : 0 - 15 (16 bit)
access : read-write
Manual Pause Parameter setting Register
address_offset : 0x1158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPAUSE : MPAUSE
bits : 0 - 15 (16 bit)
access : write-only
Reception PAUSE Frame Counter Register
address_offset : 0x1160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RPAUSE : RPAUSE
bits : 0 - 7 (8 bit)
access : read-only
PAUSE Frame Retransmission Number Of Times Setting Register
address_offset : 0x1164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPAUSE : TXPAUSE
bits : 0 - 15 (16 bit)
access : read-write
PAUSE Frame Retransmission Number Of Times Counter Register
address_offset : 0x1168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TPAUSE : TPAUSE
bits : 0 - 15 (16 bit)
access : read-only
Broadcast Frame Reception Number Of Times Setting Register
address_offset : 0x116C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCF : BCF
bits : 0 - 15 (16 bit)
access : read-write
Mac Address Register (High Rank)
address_offset : 0x11C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACADRH : MACADRH
bits : 0 - 31 (32 bit)
access : read-write
Mac Address Register (Low Rank)
address_offset : 0x11C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACADRL : MACADRL
bits : 0 - 31 (32 bit)
access : read-write
TINT1 Cunter Register
address_offset : 0x11D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TINT1CNT : TINT1CNT
bits : 0 - 31 (32 bit)
access : read-write
TINT2 Cunter Register
address_offset : 0x11D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TINT2CNT : TINT2CNT
bits : 0 - 31 (32 bit)
access : read-write
TINT3 Cunter Register
address_offset : 0x11D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TINT3CNT : TINT3CNT
bits : 0 - 31 (32 bit)
access : read-write
TINT4 Cunter Register
address_offset : 0x11DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TINT4CNT : TINT4CNT
bits : 0 - 31 (32 bit)
access : read-write
RINT1 Cunter Register
address_offset : 0x11E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RINT1CNT : RINT1CNT
bits : 0 - 31 (32 bit)
access : read-write
RINT2 Cunter Register
address_offset : 0x11E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RINT2CNT : RINT2CNT
bits : 0 - 31 (32 bit)
access : read-write
RINT3 Cunter Register
address_offset : 0x11EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RINT3CNT : RINT3CNT
bits : 0 - 31 (32 bit)
access : read-write
RINT4 Cunter Register
address_offset : 0x11F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RINT4CNT : RINT4CNT
bits : 0 - 31 (32 bit)
access : read-write
RINT5 Cunter Register
address_offset : 0x11F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RINT5CNT : RINT5CNT
bits : 0 - 31 (32 bit)
access : read-write
RINT8 Cunter Register
address_offset : 0x11F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RINT8CNT : RINT8CNT
bits : 0 - 31 (32 bit)
access : read-write
ADiC Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMDMACINT : EMDMACINT
bits : 0 - 0 (1 bit)
access : read-write
SLAVE0 : SLAVE0
bits : 8 - 8 (1 bit)
access : read-write
SLAVE1 : SLAVE1
bits : 9 - 9 (1 bit)
access : read-write
SLAVE2 : SLAVE2
bits : 10 - 10 (1 bit)
access : read-write
SLAVE3 : SLAVE3
bits : 11 - 11 (1 bit)
access : read-write
IOTOUT : IOTOUT
bits : 15 - 15 (1 bit)
access : read-write
MASTER0 : MASTER0
bits : 16 - 16 (1 bit)
access : read-write
MASTER1 : MASTER1
bits : 17 - 17 (1 bit)
access : read-write
MASTER2 : MASTER2
bits : 18 - 18 (1 bit)
access : read-write
DMATOUT : DMATOUT
bits : 23 - 23 (1 bit)
access : read-write
ADiC MODE Setting Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOTOUT : IOTOUT
bits : 8 - 8 (1 bit)
access : read-write
DMATOUT : DMATOUT
bits : 9 - 9 (1 bit)
access : read-write
DMAERR : DMAERR
bits : 10 - 10 (1 bit)
access : read-write
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