\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection : not protected
System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write
PRCK : PRCK
bits : 8 - 10 (3 bit)
access : read-write
FPSEL : FPSEL
bits : 12 - 12 (1 bit)
access : read-write
SCOSEL : SCOSEL
bits : 16 - 17 (2 bit)
access : read-write
FCSTOP : FCSTOP
bits : 20 - 20 (1 bit)
access : read-write
Peripheral Clock Stop Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK0 : MSK0
bits : 0 - 0 (1 bit)
access : read-write
MSK1 : MSK1
bits : 1 - 1 (1 bit)
access : read-write
MSK2 : MSK2
bits : 2 - 2 (1 bit)
access : read-write
MSK3 : MSK3
bits : 3 - 3 (1 bit)
access : read-write
MSK4 : MSK4
bits : 4 - 4 (1 bit)
access : read-write
MSK5 : MSK5
bits : 5 - 5 (1 bit)
access : read-write
MSK6 : MSK6
bits : 6 - 6 (1 bit)
access : read-write
MSK7 : MSK7
bits : 7 - 7 (1 bit)
access : read-write
MSK8 : MSK8
bits : 8 - 8 (1 bit)
access : read-write
MSK9 : MSK9
bits : 9 - 9 (1 bit)
access : read-write
MSK10 : MSK10
bits : 10 - 10 (1 bit)
access : read-write
MSK11 : MSK11
bits : 11 - 11 (1 bit)
access : read-write
MSK12 : MSK12
bits : 12 - 12 (1 bit)
access : read-write
MSK13 : MSK13
bits : 13 - 13 (1 bit)
access : read-write
MSK14 : MSK14
bits : 14 - 14 (1 bit)
access : read-write
MSK15 : MSK15
bits : 15 - 15 (1 bit)
access : read-write
MSK16 : MSK16
bits : 16 - 16 (1 bit)
access : read-write
MSK17 : MSK17
bits : 17 - 17 (1 bit)
access : read-write
MSK18 : MSK18
bits : 18 - 18 (1 bit)
access : read-write
MSK19 : MSK19
bits : 19 - 19 (1 bit)
access : read-write
MSK20 : MSK20
bits : 20 - 20 (1 bit)
access : read-write
MSK21 : MSK21
bits : 21 - 21 (1 bit)
access : read-write
MSK22 : MSK22
bits : 22 - 22 (1 bit)
access : read-write
MSK23 : MSK23
bits : 23 - 23 (1 bit)
access : read-write
MSK24 : MSK24
bits : 24 - 24 (1 bit)
access : read-write
MSK25 : MSK25
bits : 25 - 25 (1 bit)
access : read-write
MSK26 : MSK26
bits : 26 - 26 (1 bit)
access : read-write
MSK27 : MSK27
bits : 27 - 27 (1 bit)
access : read-write
MSK28 : MSK28
bits : 28 - 28 (1 bit)
access : read-write
MSK29 : MSK29
bits : 29 - 29 (1 bit)
access : read-write
MSK30 : MSK30
bits : 30 - 30 (1 bit)
access : read-write
MSK31 : MSK31
bits : 31 - 31 (1 bit)
access : read-write
Protect Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGPROTECT : CGPROTECT
bits : 0 - 7 (8 bit)
access : read-write
Oscillation Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUEON : WUEON
bits : 0 - 0 (1 bit)
access : write-only
WUEF : WUEF
bits : 1 - 1 (1 bit)
access : read-only
PLLON : PLLON
bits : 2 - 2 (1 bit)
access : read-write
WUPSEL1 : WUPSEL1
bits : 3 - 3 (1 bit)
access : read-write
XEN1 : XEN1
bits : 8 - 8 (1 bit)
access : read-write
XTEN : XTEN
bits : 9 - 9 (1 bit)
access : read-write
XEN3 : XEN3
bits : 10 - 10 (1 bit)
access : read-write
WUPTL : WUPTL
bits : 14 - 15 (2 bit)
access : read-write
XEN2 : XEN2
bits : 16 - 16 (1 bit)
access : read-write
OSCSEL : OSCSEL
bits : 17 - 17 (1 bit)
access : read-write
EHOSCSEL : EHOSCSEL
bits : 18 - 18 (1 bit)
access : read-write
WUPSEL2 : WUPSEL2
bits : 19 - 19 (1 bit)
access : read-write
WUPT : WUPT
bits : 20 - 31 (12 bit)
access : read-write
CG Interrupt Mode Control Register A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT0EN : INT0EN
bits : 0 - 0 (1 bit)
access : read-write
EMST0 : EMST0
bits : 2 - 3 (2 bit)
access : read-only
EMCG0 : EMCG0
bits : 4 - 6 (3 bit)
access : read-write
INT1EN : INT1EN
bits : 8 - 8 (1 bit)
access : read-write
EMST1 : EMST1
bits : 10 - 11 (2 bit)
access : read-only
EMCG1 : EMCG1
bits : 12 - 14 (3 bit)
access : read-write
INT2EN : INT2EN
bits : 16 - 16 (1 bit)
access : read-write
EMST2 : EMST2
bits : 18 - 19 (2 bit)
access : read-only
EMCG2 : EMCG2
bits : 20 - 22 (3 bit)
access : read-write
INT3EN : INT3EN
bits : 24 - 24 (1 bit)
access : read-write
EMST3 : EMST3
bits : 26 - 27 (2 bit)
access : read-only
EMCG3 : EMCG3
bits : 28 - 30 (3 bit)
access : read-write
CG Interrupt Mode Control Register B
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT4EN : INT4EN
bits : 0 - 0 (1 bit)
access : read-write
EMST4 : EMST4
bits : 2 - 3 (2 bit)
access : read-only
EMCG4 : EMCG4
bits : 4 - 6 (3 bit)
access : read-write
INT5EN : INT5EN
bits : 8 - 8 (1 bit)
access : read-write
EMST5 : EMST5
bits : 10 - 11 (2 bit)
access : read-only
EMCG5 : EMCG5
bits : 12 - 14 (3 bit)
access : read-write
INT6EN : INT6EN
bits : 16 - 16 (1 bit)
access : read-write
EMST6 : EMST6
bits : 18 - 19 (2 bit)
access : read-only
EMCG6 : EMCG6
bits : 20 - 22 (3 bit)
access : read-write
INT7EN : INT7EN
bits : 24 - 24 (1 bit)
access : read-write
EMST7 : EMST7
bits : 26 - 27 (2 bit)
access : read-only
EMCG7 : EMCG7
bits : 28 - 30 (3 bit)
access : read-write
CG Interrupt Mode Control Register C
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8EN : INT8EN
bits : 0 - 0 (1 bit)
access : read-write
EMST8 : EMST8
bits : 2 - 3 (2 bit)
access : read-only
EMCG8 : EMCG8
bits : 4 - 6 (3 bit)
access : read-write
INT9EN : INT9EN
bits : 8 - 8 (1 bit)
access : read-write
EMST9 : EMST9
bits : 10 - 11 (2 bit)
access : read-only
EMCG9 : EMCG9
bits : 12 - 14 (3 bit)
access : read-write
INTAEN : INTAEN
bits : 16 - 16 (1 bit)
access : read-write
EMSTA : EMSTA
bits : 18 - 19 (2 bit)
access : read-only
EMCGA : EMCGA
bits : 20 - 22 (3 bit)
access : read-write
INTBEN : INTBEN
bits : 24 - 24 (1 bit)
access : read-write
EMSTB : EMSTB
bits : 26 - 27 (2 bit)
access : read-only
EMCGB : EMCGB
bits : 28 - 30 (3 bit)
access : read-write
CG Interrupt Mode Control Register D
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTCEN : INTCEN
bits : 0 - 0 (1 bit)
access : read-write
EMSTC : EMSTC
bits : 2 - 3 (2 bit)
access : read-only
EMCGC : EMCGC
bits : 4 - 6 (3 bit)
access : read-write
INTDEN : INTDEN
bits : 8 - 8 (1 bit)
access : read-write
EMSTD : EMSTD
bits : 10 - 11 (2 bit)
access : read-only
EMCGD : EMCGD
bits : 12 - 14 (3 bit)
access : read-write
INTRTCEN : INTRTCEN
bits : 16 - 16 (1 bit)
access : read-write
EMSTRTC : EMSTRTC
bits : 18 - 19 (2 bit)
access : read-only
EMCGRTC : EMCGRTC
bits : 20 - 22 (3 bit)
access : read-write
INTRMCRXEN : INTRMCRXEN
bits : 24 - 24 (1 bit)
access : read-write
EMSTRMCRX : EMSTRMCRX
bits : 26 - 27 (2 bit)
access : read-only
EMCGRMCRX : EMCGRMCRX
bits : 28 - 30 (3 bit)
access : read-write
CG Interrupt Request Clear Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ICRCG : ICRCG
bits : 0 - 4 (5 bit)
access : write-only
Reset Flag Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PONRSTF : PONRSTF
bits : 0 - 0 (1 bit)
access : read-write
PINRSTF : PINRSTF
bits : 1 - 1 (1 bit)
access : read-write
WDTRSTF : WDTRSTF
bits : 2 - 2 (1 bit)
access : read-write
STOP2RSTF : STOP2RSTF
bits : 3 - 3 (1 bit)
access : read-write
DBGRSTF : DBGRSTF
bits : 4 - 4 (1 bit)
access : read-write
OFDRSTF : OFDRSTF
bits : 5 - 5 (1 bit)
access : read-write
LVDRSTF : LVDRSTF
bits : 6 - 6 (1 bit)
access : read-write
NMI Flag Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMIFLG0 : NMIFLG0
bits : 0 - 0 (1 bit)
access : read-only
NMIFLG1 : NMIFLG1
bits : 1 - 1 (1 bit)
access : read-only
NMIFLG2 : NMIFLG2
bits : 2 - 2 (1 bit)
access : read-only
NMIFLG3 : NMIFLG3
bits : 3 - 3 (1 bit)
access : read-only
Standby Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STBY : STBY
bits : 0 - 2 (3 bit)
access : read-write
DRVE : DRVE
bits : 16 - 16 (1 bit)
access : read-write
PTKEEP : PTKEEP
bits : 17 - 17 (1 bit)
access : read-write
PLL Selection Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLSEL : PLLSEL
bits : 0 - 0 (1 bit)
access : read-write
PLLSET : PLLSET
bits : 1 - 15 (15 bit)
access : read-write
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