Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
System Clock Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKIN : FRCLK input clock select
bits : 0 - 0 (1 bit)
Enumeration:
1 : CLKREF
CLKREF input
2 : EXTCLK
External Clock Input
3 : XTAL
Crystal Driver XIN/XOUT Input
0 : ROSC
Internal Ring Oscillator
End of enumeration elements list.
ACLKDIV : ACLK divider
bits : 2 - 3 (2 bit)
Enumeration:
1 : FCLK /2
ACLK = FCLK /2
2 : FCLK /4
ACLK = FCLK /4
3 : FCLK /8
ACLK = FCLK /8
4 : FCLK /16
ACLK = FCLK /16
5 : FCLK /32
ACLK = FCLK /32
6 : FCLK /64
ACLK = FCLK /64
7 : FCLK /128
ACLK = FCLK /128
0 : FCLK /1
ACLK = FCLK /1
End of enumeration elements list.
HCLKDIV : HCLK divider
bits : 5 - 5 (1 bit)
Enumeration:
1 : FCLK /2
HCLK = FCLK /2
2 : FCLK /4
HCLK = FCLK /4
3 : FCLK /8
HCLK = FCLK /8
0 : FCLK /1
HCLK = FCLK /1
End of enumeration elements list.
FCLK : FCLK input clock select
bits : 7 - 6 (0 bit)
Enumeration:
1 : PLLOUT
FCLK = PLLOUT clock
0 : FRCLK
FCLK = FRCLK
End of enumeration elements list.
PLL Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLEN : PLL enable
bits : 0 - -1 (0 bit)
Enumeration:
1 : enable
Enable PLL
0 : disable
Disable PLL
End of enumeration elements list.
PLLINDIV : PLL Input Divider (divider = /[value+2])
bits : 2 - 5 (4 bit)
Enumeration:
0 : /2
PLL input divider: /2
End of enumeration elements list.
PLLFBDIV : PLL Feedback Divider (divider = /[value + 2])
bits : 7 - 14 (8 bit)
Enumeration:
0 : /2
PLL feedback divider: /2
End of enumeration elements list.
PLLOUTDIV : PLL Output Divider (divider = /[value+1], 0 reserved)
bits : 16 - 18 (3 bit)
Enumeration:
1 : /1
PLL output divider: /1
End of enumeration elements list.
Ring Oscillator Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROSCEN : Ring Oscillator Enable
bits : 0 - -1 (0 bit)
Enumeration:
1 : enable
Enable Ring Oscillator
0 : disable
Disable Ring Oscillator
End of enumeration elements list.
ROSCP : Ring Oscillator Frequency Setting
bits : 1 - 1 (1 bit)
Enumeration:
1 : 15.3 MHz
Set Ring Oscillator to 15.3 MHz
2 : 10.7 MHz
Set Ring Oscillator to 10.7 MHz
3 : 8.3 MHz
Set Ring Oscillator to 8.3 MHz
0 : 28.7 MHz
Set Ring Oscillator to 28.7 MHz
End of enumeration elements list.
Crystal Driver Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTALEN : Enable XTAL driver
bits : 0 - -1 (0 bit)
Enumeration:
1 : enable
Enable XTAL Driver
0 : disable
Disable XTAL Driver
End of enumeration elements list.
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