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TIMERA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TxCTL

TxPRD

TxCC0CTL

TxCC0CTR

TxCC1CTL

TxCC1CTR

TxCC2CTL

TxCC2CTR

TxCC3CTL

TxCC3CTR

TxCC4CTL

TxCC4CTR

TxCC5CTL

TxCC5CTR

TxCC6CTL

TxCC6CTR

TxCC7CTL

TxCC7CTR

TxCTR

DTGA0CTL

DTGA0LED

DTGA0TED

DTGA1CTL

DTGA1LED

DTGA1TED

DTGA2CTL

DTGA2LED

DTGA2TED

DTGA3CTL

DTGA3LED

DTGA3TED


TxCTL

Timer Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCTL TxCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRDL CLR SS INT INTEN CLKDIV CLK MODE DTGCLK

PRDL : Timer Period Latch
bits : 0 - -1 (0 bit)

Enumeration:

0 : period

Latch timer values counting up at TxPRD-1

1 : wrap

Latch timer values when counting down to 1

End of enumeration elements list.

CLR : Timer clear
bits : 2 - 1 (0 bit)

Enumeration:

0 : clear

Clear Timer, hold in reset, set SYNC_OUT

1 : noclear

Do not clear timer, clear SYNC_OUT

End of enumeration elements list.

SS : Timer single shot
bits : 3 - 2 (0 bit)

Enumeration:

0 : continuous

Continuous mode

1 : single

Single shot mode

0 : continuous

Continuous mode

0 : continuous

Continuous mode

0 : continuous

Continuous mode

End of enumeration elements list.

INT : Timer interrupt
bits : 4 - 3 (0 bit)

Enumeration:

0 : interrupt

interrupt flag, write 1 to clear

1 : noint

No interrupt

End of enumeration elements list.

INTEN : Timer interrupt enable
bits : 5 - 4 (0 bit)

Enumeration:

0 : enabled

timer interrupt enabled

1 : disabled

timer interrupt disabled

End of enumeration elements list.

CLKDIV : timer clock divider
bits : 6 - 7 (2 bit)

Enumeration:

0 : /1

divide by 1

1 : /2

divide by 2

2 : /4

divide by 4

3 : /8

divide by 8

4 : /16

divide by 16

5 : /32

divide by 32

6 : /64

divide by 64

7 : /128

divide by 128

End of enumeration elements list.

CLK : timer clock input source
bits : 9 - 8 (0 bit)

Enumeration:

0 : HCLK

HCLK

1 : ACLK

ACLK

End of enumeration elements list.

MODE : timer mode
bits : 10 - 10 (1 bit)

Enumeration:

0 : disabled

timer disabled

1 : up

up mode

2 : updown

up/down mode

End of enumeration elements list.

DTGCLK : DTG clock select
bits : 13 - 12 (0 bit)

Enumeration:

0 : CLK

DTG uses clock selected by TxTCL.CLK

1 : CLKDIV

DTG uses clock selected by TxCTL.CLKDIV

End of enumeration elements list.


TxPRD

timer period
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxPRD TxPRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD : timer period value
bits : 0 - 14 (15 bit)


TxCC0CTL

timer capture and compare control unit 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC0CTL TxCC0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCEDG CCINT CCINTEN CCMODE

CCEDG : capture mode edge detect
bits : 0 - 0 (1 bit)

Enumeration:

0 : hitolow

high to low transition only

1 : lowtohigh

low to high transitions only

2 : both

both high to low and low to high transitions

End of enumeration elements list.

CCINT : capture and compare interrupt
bits : 2 - 1 (0 bit)

Enumeration:

0 : none

no interrupt detected

1 : interrupt

interrupt, write 1b to clear

End of enumeration elements list.

CCINTEN : capture and compare interrupt enable
bits : 3 - 2 (0 bit)

Enumeration:

0 : disabled

interrupt disabled

1 : enabled

interrupt enabled

End of enumeration elements list.

CCMODE : capture and compare mode
bits : 4 - 3 (0 bit)

Enumeration:

0 : compare mode

compare mode

1 : capture mode

capture mode

End of enumeration elements list.


TxCC0CTR

capture and compare counter unit 0
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC0CTR TxCC0CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCCTR

CCCTR : capture and compare counter value
bits : 0 - 14 (15 bit)


TxCC1CTL

timer capture and compare control unit 0
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC1CTL TxCC1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCEDG CCINT CCINTEN CCMODE

CCEDG : capture mode edge detect
bits : 0 - 0 (1 bit)

Enumeration:

0 : hitolow

high to low transition only

1 : lowtohigh

low to high transitions only

2 : both

both high to low and low to high transitions

End of enumeration elements list.

CCINT : capture and compare interrupt
bits : 2 - 1 (0 bit)

Enumeration:

0 : none

no interrupt detected

1 : interrupt

interrupt, write 1b to clear

End of enumeration elements list.

CCINTEN : capture and compare interrupt enable
bits : 3 - 2 (0 bit)

Enumeration:

0 : disabled

interrupt disabled

1 : enabled

interrupt enabled

End of enumeration elements list.

CCMODE : capture and compare mode
bits : 4 - 3 (0 bit)

Enumeration:

0 : compare mode

compare mode

1 : capture mode

capture mode

End of enumeration elements list.


TxCC1CTR

capture and compare counter unit 1
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC1CTR TxCC1CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC2CTL

timer capture and compare control unit 2
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC2CTL TxCC2CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC2CTR

capture and compare counter unit 2
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC2CTR TxCC2CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC3CTL

timer capture and compare control unit 3
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC3CTL TxCC3CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC3CTR

capture and compare counter unit 3
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC3CTR TxCC3CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC4CTL

timer capture and compare control unit 4
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC4CTL TxCC4CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC4CTR

capture and compare counter unit 4
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC4CTR TxCC4CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC5CTL

timer capture and compare control unit 5
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC5CTL TxCC5CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC5CTR

capture and compare counter unit 5
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC5CTR TxCC5CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC6CTL

timer capture and compare control unit 6
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC6CTL TxCC6CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC6CTR

capture and compare counter unit 6
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC6CTR TxCC6CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC7CTL

timer capture and compare control unit 7
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC7CTL TxCC7CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC7CTR

capture and compare counter unit 7
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC7CTR TxCC7CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCTR

timer counter
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TxCTR TxCTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTR

CTR : timer counter value
bits : 0 - 14 (15 bit)


DTGA0CTL

Timer A dead-time generator control unit 0
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA0CTL DTGA0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVLS INVHS OTP BYPASS

INVLS : Invert low-side output signal
bits : 4 - 3 (0 bit)

Enumeration:

0 : disabled

do not invert low-side output signal

1 : enabled

invert low-side output signal

End of enumeration elements list.

INVHS : Invert high-side output signal
bits : 5 - 4 (0 bit)

Enumeration:

0 : disabled

do not invert high-side output signal

1 : enabled

invert high-side output signal

End of enumeration elements list.

OTP : On-time preservation
bits : 6 - 5 (0 bit)

Enumeration:

0 : disabled

do not extend on time

1 : enabled

extend on time

End of enumeration elements list.

BYPASS : bypass dead-time generation
bits : 7 - 6 (0 bit)

Enumeration:

0 : disabled

do not bypass dead-time generation

1 : enabled

bypass dead-time generation

End of enumeration elements list.


DTGA0LED

Timer A dead-time generator leading-edge delay counter unit 0
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA0LED DTGA0LED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LED

LED : leading-edge delay counter
bits : 0 - 10 (11 bit)


DTGA0TED

Timer A dead-time generator trailing-edge delay counter unit 0
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA0TED DTGA0TED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TED

TED : trailing-edge delay counter
bits : 0 - 10 (11 bit)


DTGA1CTL

Timer A dead-time generator control unit 1
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA1CTL DTGA1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVLS INVHS OTP BYPASS

INVLS : Invert low-side output signal
bits : 4 - 3 (0 bit)

Enumeration:

0 : disabled

do not invert low-side output signal

1 : enabled

invert low-side output signal

End of enumeration elements list.

INVHS : Invert high-side output signal
bits : 5 - 4 (0 bit)

Enumeration:

0 : disabled

do not invert high-side output signal

1 : enabled

invert high-side output signal

End of enumeration elements list.

OTP : On-time preservation
bits : 6 - 5 (0 bit)

Enumeration:

0 : disabled

do not extend on time

1 : enabled

extend on time

End of enumeration elements list.

BYPASS : bypass dead-time generation
bits : 7 - 6 (0 bit)

Enumeration:

0 : disabled

do not bypass dead-time generation

1 : enabled

bypass dead-time generation

End of enumeration elements list.


DTGA1LED

Timer A dead-time generator leading-edge delay counter unit 1
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA1LED DTGA1LED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LED

LED : leading-edge delay counter
bits : 0 - 10 (11 bit)


DTGA1TED

Timer A dead-time generator trailing-edge delay counter unit 1
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA1TED DTGA1TED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TED

TED : trailing-edge delay counter
bits : 0 - 10 (11 bit)


DTGA2CTL

Timer A dead-time generator control unit 2
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA2CTL DTGA2CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVLS INVHS OTP BYPASS

INVLS : Invert low-side output signal
bits : 4 - 3 (0 bit)

Enumeration:

0 : disabled

do not invert low-side output signal

1 : enabled

invert low-side output signal

End of enumeration elements list.

INVHS : Invert high-side output signal
bits : 5 - 4 (0 bit)

Enumeration:

0 : disabled

do not invert high-side output signal

1 : enabled

invert high-side output signal

End of enumeration elements list.

OTP : On-time preservation
bits : 6 - 5 (0 bit)

Enumeration:

0 : disabled

do not extend on time

1 : enabled

extend on time

End of enumeration elements list.

BYPASS : bypass dead-time generation
bits : 7 - 6 (0 bit)

Enumeration:

0 : disabled

do not bypass dead-time generation

1 : enabled

bypass dead-time generation

End of enumeration elements list.


DTGA2LED

Timer A dead-time generator leading-edge delay counter unit 2
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA2LED DTGA2LED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LED

LED : leading-edge delay counter
bits : 0 - 10 (11 bit)


DTGA2TED

Timer A dead-time generator trailing-edge delay counter unit 2
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA2TED DTGA2TED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TED

TED : trailing-edge delay counter
bits : 0 - 10 (11 bit)


DTGA3CTL

Timer A dead-time generator control unit 3
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA3CTL DTGA3CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVLS INVHS OTP BYPASS

INVLS : Invert low-side output signal
bits : 4 - 3 (0 bit)

Enumeration:

0 : disabled

do not invert low-side output signal

1 : enabled

invert low-side output signal

End of enumeration elements list.

INVHS : Invert high-side output signal
bits : 5 - 4 (0 bit)

Enumeration:

0 : disabled

do not invert high-side output signal

1 : enabled

invert high-side output signal

End of enumeration elements list.

OTP : On-time preservation
bits : 6 - 5 (0 bit)

Enumeration:

0 : disabled

do not extend on time

1 : enabled

extend on time

End of enumeration elements list.

BYPASS : bypass dead-time generation
bits : 7 - 6 (0 bit)

Enumeration:

0 : disabled

do not bypass dead-time generation

1 : enabled

bypass dead-time generation

End of enumeration elements list.


DTGA3LED

Timer A dead-time generator leading-edge delay counter unit 3
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA3LED DTGA3LED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LED

LED : leading-edge delay counter
bits : 0 - 10 (11 bit)


DTGA3TED

Timer A dead-time generator trailing-edge delay counter unit 0
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGA3TED DTGA3TED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TED

TED : trailing-edge delay counter
bits : 0 - 10 (11 bit)



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