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TIMERD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TxCTL

TxPRD

TxCC0CTL

TxCC0CTR

TxCC1CTL

TxCC1CTR

TxCTR

DTGD0CTL

DTGD0LED

DTGD0TED


TxCTL

Timer Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCTL TxCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRDL CLR SS INT INTEN CLKDIV CLK MODE DTGCLK

PRDL : Timer Period Latch
bits : 0 - -1 (0 bit)

Enumeration:

0 : period

Latch timer values counting up at TxPRD-1

1 : wrap

Latch timer values when counting down to 1

End of enumeration elements list.

CLR : Timer clear
bits : 2 - 1 (0 bit)

Enumeration:

0 : clear

Clear Timer, hold in reset, set SYNC_OUT

1 : noclear

Do not clear timer, clear SYNC_OUT

End of enumeration elements list.

SS : Timer single shot
bits : 3 - 2 (0 bit)

Enumeration:

0 : continuous

Continuous mode

1 : single

Single shot mode

0 : continuous

Continuous mode

0 : continuous

Continuous mode

0 : continuous

Continuous mode

End of enumeration elements list.

INT : Timer interrupt
bits : 4 - 3 (0 bit)

Enumeration:

0 : interrupt

interrupt flag, write 1 to clear

1 : noint

No interrupt

End of enumeration elements list.

INTEN : Timer interrupt enable
bits : 5 - 4 (0 bit)

Enumeration:

0 : enabled

timer interrupt enabled

1 : disabled

timer interrupt disabled

End of enumeration elements list.

CLKDIV : timer clock divider
bits : 6 - 7 (2 bit)

Enumeration:

0 : /1

divide by 1

1 : /2

divide by 2

2 : /4

divide by 4

3 : /8

divide by 8

4 : /16

divide by 16

5 : /32

divide by 32

6 : /64

divide by 64

7 : /128

divide by 128

End of enumeration elements list.

CLK : timer clock input source
bits : 9 - 8 (0 bit)

Enumeration:

0 : HCLK

HCLK

1 : ACLK

ACLK

End of enumeration elements list.

MODE : timer mode
bits : 10 - 10 (1 bit)

Enumeration:

0 : disabled

timer disabled

1 : up

up mode

2 : updown

up/down mode

End of enumeration elements list.

DTGCLK : DTG clock select
bits : 13 - 12 (0 bit)

Enumeration:

0 : CLK

DTG uses clock selected by TxTCL.CLK

1 : CLKDIV

DTG uses clock selected by TxCTL.CLKDIV

End of enumeration elements list.


TxPRD

timer period
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxPRD TxPRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD : timer period value
bits : 0 - 14 (15 bit)


TxCC0CTL

timer capture and compare control unit 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC0CTL TxCC0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCEDG CCINT CCINTEN CCMODE

CCEDG : capture mode edge detect
bits : 0 - 0 (1 bit)

Enumeration:

0 : hitolow

high to low transition only

1 : lowtohigh

low to high transitions only

2 : both

both high to low and low to high transitions

End of enumeration elements list.

CCINT : capture and compare interrupt
bits : 2 - 1 (0 bit)

Enumeration:

0 : none

no interrupt detected

1 : interrupt

interrupt, write 1b to clear

End of enumeration elements list.

CCINTEN : capture and compare interrupt enable
bits : 3 - 2 (0 bit)

Enumeration:

0 : disabled

interrupt disabled

1 : enabled

interrupt enabled

End of enumeration elements list.

CCMODE : capture and compare mode
bits : 4 - 3 (0 bit)

Enumeration:

0 : compare mode

compare mode

1 : capture mode

capture mode

End of enumeration elements list.


TxCC0CTR

capture and compare counter unit 0
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC0CTR TxCC0CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCCTR

CCCTR : capture and compare counter value
bits : 0 - 14 (15 bit)


TxCC1CTL

timer capture and compare control unit 1
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC1CTL TxCC1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCC1CTR

capture and compare counter unit 1
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TxCC1CTR TxCC1CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCTR

timer counter
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TxCTR TxCTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTR

CTR : timer counter value
bits : 0 - 14 (15 bit)


DTGD0CTL

Timer A dead-time generator control unit 0
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGD0CTL DTGD0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVLS INVHS OTP BYPASS

INVLS : Invert low-side output signal
bits : 4 - 3 (0 bit)

Enumeration:

0 : disabled

do not invert low-side output signal

1 : enabled

invert low-side output signal

End of enumeration elements list.

INVHS : Invert high-side output signal
bits : 5 - 4 (0 bit)

Enumeration:

0 : disabled

do not invert high-side output signal

1 : enabled

invert high-side output signal

End of enumeration elements list.

OTP : On-time preservation
bits : 6 - 5 (0 bit)

Enumeration:

0 : disabled

do not extend on time

1 : enabled

extend on time

End of enumeration elements list.

BYPASS : bypass dead-time generation
bits : 7 - 6 (0 bit)

Enumeration:

0 : disabled

do not bypass dead-time generation

1 : enabled

bypass dead-time generation

End of enumeration elements list.


DTGD0LED

Timer A dead-time generator leading-edge delay counter unit 0
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGD0LED DTGD0LED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LED

LED : leading-edge delay counter
bits : 0 - 10 (11 bit)


DTGD0TED

Timer A dead-time generator trailing-edge delay counter unit 0
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGD0TED DTGD0TED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TED

TED : trailing-edge delay counter
bits : 0 - 10 (11 bit)



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