Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SOC Bus Bridge Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSEN : SOC bus bridge enable
bits : 0 - -1 (0 bit)
Enumeration:
0 : disable
disable this module
1 : enable
enable this module
End of enumeration elements list.
SIE : SOC bus bridge interrupt enable
bits : 1 - 0 (0 bit)
Enumeration:
0 : disable
disable interrupts
1 : enable
enable interrupts
End of enumeration elements list.
MTRARM : MTRANS re-arm
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
1 : re-arm
re-arms the SOCBCTL.MTRANS operation by de-asserting CSx chip select and returning the master mode state machine to IDLE.
End of enumeration elements list.
SOC Bus Bridge Status
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOCB_INT : SOC bus bridge interrupt
bits : 0 - -1 (0 bit)
Enumeration:
0 : none
no interrupt
1 : interrupt
interrupt
End of enumeration elements list.
RDOFL : Read buffer overflow
bits : 2 - 1 (0 bit)
Enumeration:
0 : none
no read overflow since bit cleared
1 : overflow
read overflow detected, write 1 to clear
End of enumeration elements list.
CYC_DONE : Cycle done (current transfer is complete)
bits : 5 - 4 (0 bit)
Enumeration:
0 : not done
No cycle done detected since this bit was cleared
1 : completed
Cycle done detected, write one to clear
End of enumeration elements list.
WRUFL : Write buffer underflow
bits : 8 - 7 (0 bit)
Enumeration:
0 : none
No write buffer underflow detected since this bit was cleared
1 : underflow
Write buffer underflow detected, write one to clear
End of enumeration elements list.
TXFULL : Transmit holding register in use
bits : 9 - 8 (0 bit)
Enumeration:
0 : ready
TX transmit holding register ready to accept data word
1 : not ready
TX transmit holding register in use and not ready
End of enumeration elements list.
RXFULL : Receive holding register in use
bits : 10 - 9 (0 bit)
Enumeration:
0 : empty
RX incoming holding register contains no valid data word
1 : full
RX incoming holding register contains a valid data word
End of enumeration elements list.
CURSTATE : Raw status of the SOC bus bridge master state machine's 'current_state' register
bits : 12 - 13 (2 bit)
Enumeration:
0 : IDLE
IDLE
1 : CSSETUP
CSSETUP
2 : TRANSFER
TRANSFER
3 : CSHOLD
CSHOLD
4 : CSWAIT
CSWAIT
5 : CKWAIT
CKWAIT
6 : MTRANS
MTRANS
7 : CSBEGIN
CSBEGIN
End of enumeration elements list.
SOC Bus Bridge Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SOC bus bridge data
bits : 0 - 6 (7 bit)
SOC Bus Bridge Interrupt Enable
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDOFL_EN : Read buffer overflow RDOFL interrupt enable
bits : 2 - 1 (0 bit)
Enumeration:
0 : disable
disable SOCBSTAT.RDOFL interrupt
1 : enable
enable SOCBSTAT.RDOFL interrupt
End of enumeration elements list.
WRUFL_EN : Write buffer underflow SOCBSTAT.WRUFL interrupt enable
bits : 8 - 7 (0 bit)
Enumeration:
0 : disable
disable SOCBSTAT.WRUFL interrupt
1 : enable
enable SOCBSTAT.WRUFL interrupt
End of enumeration elements list.
SOC Bus Bridge Configuration
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRST : Module reset
bits : 2 - 1 (0 bit)
Enumeration:
0 : disable
do not hold the module in reset
1 : reset
force soft reset of module. The internal state machines are reset status register is cleared however, the soft reset does not affect control register values.
End of enumeration elements list.
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