TimerD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

add a new register to this peripheral

CTL

QEPCTL

CCTL0

CCTR0

CCTL1

CCTR1

CCTL2

CCTR2

CCTL3

CCTR3

CCTL4

CCTR4

CCTL5

CCTR5

CCTL6

CCTR6

CCTL7

CCTR7

DTGCTL0

DTGCTL1

DTGCTL2

DTGCTL3

INT

PRD

CTR


CTL

Timer D Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PRDLATCH SSYNC SINGLE CLKDIV CLKSRC DTGCLK LATCH CLR BASEIE

MODE : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : Disabled

Disabled Mode

1 : Up

Up Mode

2 : Up/Down

Up/Down Mode

3 : Asymmetric

Asymmetric Mode

End of enumeration elements list.

PRDLATCH : Timer Period Latch Mode
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : CTR=0

Period is latched when CTR = 0

1 : CTR=Period

Period is latched when CTR = Period

2 : Immediate

Period is latched immediately upon register write

End of enumeration elements list.

SSYNC : Timer Slave Synchronization
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disabled

Slave Sync Disabled

1 : Enabled

Slave Sync Enabled

End of enumeration elements list.

SINGLE : Single Shot Timer
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : Disabled

Single Shot Disabled (auto-reload)

1 : Enabled

Single Shot Timer Enabled

End of enumeration elements list.

CLKDIV : Timer Input Clock Divider
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

0 : /1

Timer input clock /1

1 : /2

Timer input clock /2

2 : /4

Timer input clock /4

3 : /8

Timer input clock /8

4 : /16

Timer input clock /16

5 : /32

Timer input clock /32

6 : /64

Timer input clock /64

7 : /128

Timer input clock /128

End of enumeration elements list.

CLKSRC : Timer Clock Source
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : PCLK

PCLK selected as input to timer

1 : ACLK

ACLK selected as input to timer

End of enumeration elements list.

DTGCLK : Dead-Time Generator Clock Source
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : Before Divider

Before input clock divider

1 : After Divider

After input clock divider

End of enumeration elements list.

LATCH : Write 1 to Latch Period and all CCTRs
bits : 11 - 22 (12 bit)
access : read-write

CLR : Timer Clear
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : Do Not Clear

Do not clear timer counter

1 : Clear

Clear timer counter

End of enumeration elements list.

BASEIE : Base timer interrupt enable
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : Disabled

Base interrupt disabled

1 : Enabled

Base interrupt enabled

End of enumeration elements list.


QEPCTL

Timer D QEP Control
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QEPCTL QEPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCTL0

Timer D CC Control 0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL0 CCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CCINTEN CCINTEDGE CCOUTINV CCLATCH CCFORCE CCINTSKIP

MODE : CCR Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Compare

Compare Mode

1 : Capture

Capture Mode

End of enumeration elements list.

CCINTEN : CCR Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disabled

CCR interrupt disabled

1 : Enabled

CCR interrupt enabled

End of enumeration elements list.

CCINTEDGE : Capture Mode Interrupt Edge Setting
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : Rising

Rising Edge Interrupt

1 : Falling

Falling Edge Interrupt

2 : Both

Rising and Falling Edge Interrupt

End of enumeration elements list.

CCOUTINV : Invert CCR Output
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Not Inverted

Do not invert CCR output

1 : Inverted

Invert CCR output

End of enumeration elements list.

CCLATCH : CCR Register Latch Mode
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : CTR=0/Rising

Compare(latch on CTR=0)/ Capture(latch on rising edge)

1 : CTR=Period/Falling

Compare(latch on CTR=Period)/ Capture(latch on falling edge)

2 : Immediate/Both

Compare(latch immediately)/ Capture(latch on both edges)

End of enumeration elements list.

CCFORCE : Write 1 to force compare event (self-clearing)
bits : 7 - 14 (8 bit)
access : read-write

CCINTSKIP : CC Interrupt Skip Counter
bits : 8 - 19 (12 bit)
access : read-write

Enumeration:

0 : Don't Skip

Don't skip CCR matches before interrupt

1 : Skip 1

Skip 1 CCR match before interrupt

2 : Skip 2

Skip 2 CCR matches before interrupt

3 : Skip 3

Skip 3 CCR matches before interrupt

4 : Skip 4

Skip 4 CCR matches before interrupt

5 : Skip 5

Skip 5 CCR matches before interrupt

6 : Skip 6

Skip 6 CCR matches before interrupt

7 : Skip 7

Skip 7 CCR matches before interrupt

8 : Skip 8

Skip 8 CCR matches before interrupt

9 : Skip 9

Skip 9 CCR matches before interrupt

10 : Skip 10

Skip 10 CCR matches before interrupt

11 : Skip 11

Skip 11 CCR matches before interrupt

12 : Skip 12

Skip 12 CCR matches before interrupt

13 : Skip 13

Skip 13 CCR matches before interrupt

14 : Skip 14

Skip 14 CCR matches before interrupt

15 : Skip 15

Skip 15 CCR matches before interrupt

End of enumeration elements list.


CCTR0

Timer D CC Counter 0
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTR0 CCTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCTL1

Timer D CC Control 1
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL1 CCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CCINTEN CCINTEDGE CCOUTINV CCLATCH CCFORCE CCINTSKIP

MODE : CCR Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Compare

Compare Mode

1 : Capture

Capture Mode

End of enumeration elements list.

CCINTEN : CCR Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disabled

CCR interrupt disabled

1 : Enabled

CCR interrupt enabled

End of enumeration elements list.

CCINTEDGE : Capture Mode Interrupt Edge Setting
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : Rising

Rising Edge Interrupt

1 : Falling

Falling Edge Interrupt

2 : Both

Rising and Falling Edge Interrupt

End of enumeration elements list.

CCOUTINV : Invert CCR Output
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Not Inverted

Do not invert CCR output

1 : Inverted

Invert CCR output

End of enumeration elements list.

CCLATCH : CCR Register Latch Mode
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : CTR=0/Rising

Compare(latch on CTR=0)/ Capture(latch on rising edge)

1 : CTR=Period/Falling

Compare(latch on CTR=Period)/ Capture(latch on falling edge)

2 : Immediate/Both

Compare(latch immediately)/ Capture(latch on both edges)

End of enumeration elements list.

CCFORCE : Write 1 to force compare event (self-clearing)
bits : 7 - 14 (8 bit)
access : read-write

CCINTSKIP : CC Interrupt Skip Counter
bits : 8 - 19 (12 bit)
access : read-write

Enumeration:

0 : Don't Skip

Don't skip CCR matches before interrupt

1 : Skip 1

Skip 1 CCR match before interrupt

2 : Skip 2

Skip 2 CCR matches before interrupt

3 : Skip 3

Skip 3 CCR matches before interrupt

4 : Skip 4

Skip 4 CCR matches before interrupt

5 : Skip 5

Skip 5 CCR matches before interrupt

6 : Skip 6

Skip 6 CCR matches before interrupt

7 : Skip 7

Skip 7 CCR matches before interrupt

8 : Skip 8

Skip 8 CCR matches before interrupt

9 : Skip 9

Skip 9 CCR matches before interrupt

10 : Skip 10

Skip 10 CCR matches before interrupt

11 : Skip 11

Skip 11 CCR matches before interrupt

12 : Skip 12

Skip 12 CCR matches before interrupt

13 : Skip 13

Skip 13 CCR matches before interrupt

14 : Skip 14

Skip 14 CCR matches before interrupt

15 : Skip 15

Skip 15 CCR matches before interrupt

End of enumeration elements list.


CCTR1

Timer D CC Counter 1
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTR1 CCTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCTL2

Timer D CC Control 2
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL2 CCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CCINTEN CCINTEDGE CCOUTINV CCLATCH CCFORCE CCINTSKIP

MODE : CCR Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Compare

Compare Mode

1 : Capture

Capture Mode

End of enumeration elements list.

CCINTEN : CCR Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disabled

CCR interrupt disabled

1 : Enabled

CCR interrupt enabled

End of enumeration elements list.

CCINTEDGE : Capture Mode Interrupt Edge Setting
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : Rising

Rising Edge Interrupt

1 : Falling

Falling Edge Interrupt

2 : Both

Rising and Falling Edge Interrupt

End of enumeration elements list.

CCOUTINV : Invert CCR Output
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Not Inverted

Do not invert CCR output

1 : Inverted

Invert CCR output

End of enumeration elements list.

CCLATCH : CCR Register Latch Mode
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : CTR=0/Rising

Compare(latch on CTR=0)/ Capture(latch on rising edge)

1 : CTR=Period/Falling

Compare(latch on CTR=Period)/ Capture(latch on falling edge)

2 : Immediate/Both

Compare(latch immediately)/ Capture(latch on both edges)

End of enumeration elements list.

CCFORCE : Write 1 to force compare event (self-clearing)
bits : 7 - 14 (8 bit)
access : read-write

CCINTSKIP : CC Interrupt Skip Counter
bits : 8 - 19 (12 bit)
access : read-write

Enumeration:

0 : Don't Skip

Don't skip CCR matches before interrupt

1 : Skip 1

Skip 1 CCR match before interrupt

2 : Skip 2

Skip 2 CCR matches before interrupt

3 : Skip 3

Skip 3 CCR matches before interrupt

4 : Skip 4

Skip 4 CCR matches before interrupt

5 : Skip 5

Skip 5 CCR matches before interrupt

6 : Skip 6

Skip 6 CCR matches before interrupt

7 : Skip 7

Skip 7 CCR matches before interrupt

8 : Skip 8

Skip 8 CCR matches before interrupt

9 : Skip 9

Skip 9 CCR matches before interrupt

10 : Skip 10

Skip 10 CCR matches before interrupt

11 : Skip 11

Skip 11 CCR matches before interrupt

12 : Skip 12

Skip 12 CCR matches before interrupt

13 : Skip 13

Skip 13 CCR matches before interrupt

14 : Skip 14

Skip 14 CCR matches before interrupt

15 : Skip 15

Skip 15 CCR matches before interrupt

End of enumeration elements list.


CCTR2

Timer D CC Counter 2
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTR2 CCTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCTL3

Timer D CC Control 3
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL3 CCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CCINTEN CCINTEDGE CCOUTINV CCLATCH CCFORCE CCINTSKIP

MODE : CCR Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Compare

Compare Mode

1 : Capture

Capture Mode

End of enumeration elements list.

CCINTEN : CCR Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disabled

CCR interrupt disabled

1 : Enabled

CCR interrupt enabled

End of enumeration elements list.

CCINTEDGE : Capture Mode Interrupt Edge Setting
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : Rising

Rising Edge Interrupt

1 : Falling

Falling Edge Interrupt

2 : Both

Rising and Falling Edge Interrupt

End of enumeration elements list.

CCOUTINV : Invert CCR Output
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Not Inverted

Do not invert CCR output

1 : Inverted

Invert CCR output

End of enumeration elements list.

CCLATCH : CCR Register Latch Mode
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : CTR=0/Rising

Compare(latch on CTR=0)/ Capture(latch on rising edge)

1 : CTR=Period/Falling

Compare(latch on CTR=Period)/ Capture(latch on falling edge)

2 : Immediate/Both

Compare(latch immediately)/ Capture(latch on both edges)

End of enumeration elements list.

CCFORCE : Write 1 to force compare event (self-clearing)
bits : 7 - 14 (8 bit)
access : read-write

CCINTSKIP : CC Interrupt Skip Counter
bits : 8 - 19 (12 bit)
access : read-write

Enumeration:

0 : Don't Skip

Don't skip CCR matches before interrupt

1 : Skip 1

Skip 1 CCR match before interrupt

2 : Skip 2

Skip 2 CCR matches before interrupt

3 : Skip 3

Skip 3 CCR matches before interrupt

4 : Skip 4

Skip 4 CCR matches before interrupt

5 : Skip 5

Skip 5 CCR matches before interrupt

6 : Skip 6

Skip 6 CCR matches before interrupt

7 : Skip 7

Skip 7 CCR matches before interrupt

8 : Skip 8

Skip 8 CCR matches before interrupt

9 : Skip 9

Skip 9 CCR matches before interrupt

10 : Skip 10

Skip 10 CCR matches before interrupt

11 : Skip 11

Skip 11 CCR matches before interrupt

12 : Skip 12

Skip 12 CCR matches before interrupt

13 : Skip 13

Skip 13 CCR matches before interrupt

14 : Skip 14

Skip 14 CCR matches before interrupt

15 : Skip 15

Skip 15 CCR matches before interrupt

End of enumeration elements list.


CCTR3

Timer D CC Counter 3
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTR3 CCTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCTL4

Timer D CC Control 4
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL4 CCTL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CCINTEN CCINTEDGE CCOUTINV CCLATCH CCFORCE CCINTSKIP

MODE : CCR Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Compare

Compare Mode

1 : Capture

Capture Mode

End of enumeration elements list.

CCINTEN : CCR Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disabled

CCR interrupt disabled

1 : Enabled

CCR interrupt enabled

End of enumeration elements list.

CCINTEDGE : Capture Mode Interrupt Edge Setting
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : Rising

Rising Edge Interrupt

1 : Falling

Falling Edge Interrupt

2 : Both

Rising and Falling Edge Interrupt

End of enumeration elements list.

CCOUTINV : Invert CCR Output
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Not Inverted

Do not invert CCR output

1 : Inverted

Invert CCR output

End of enumeration elements list.

CCLATCH : CCR Register Latch Mode
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : CTR=0/Rising

Compare(latch on CTR=0)/ Capture(latch on rising edge)

1 : CTR=Period/Falling

Compare(latch on CTR=Period)/ Capture(latch on falling edge)

2 : Immediate/Both

Compare(latch immediately)/ Capture(latch on both edges)

End of enumeration elements list.

CCFORCE : Write 1 to force compare event (self-clearing)
bits : 7 - 14 (8 bit)
access : read-write

CCINTSKIP : CC Interrupt Skip Counter
bits : 8 - 19 (12 bit)
access : read-write

Enumeration:

0 : Don't Skip

Don't skip CCR matches before interrupt

1 : Skip 1

Skip 1 CCR match before interrupt

2 : Skip 2

Skip 2 CCR matches before interrupt

3 : Skip 3

Skip 3 CCR matches before interrupt

4 : Skip 4

Skip 4 CCR matches before interrupt

5 : Skip 5

Skip 5 CCR matches before interrupt

6 : Skip 6

Skip 6 CCR matches before interrupt

7 : Skip 7

Skip 7 CCR matches before interrupt

8 : Skip 8

Skip 8 CCR matches before interrupt

9 : Skip 9

Skip 9 CCR matches before interrupt

10 : Skip 10

Skip 10 CCR matches before interrupt

11 : Skip 11

Skip 11 CCR matches before interrupt

12 : Skip 12

Skip 12 CCR matches before interrupt

13 : Skip 13

Skip 13 CCR matches before interrupt

14 : Skip 14

Skip 14 CCR matches before interrupt

15 : Skip 15

Skip 15 CCR matches before interrupt

End of enumeration elements list.


CCTR4

Timer D CC Counter 4
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTR4 CCTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCTL5

Timer D CC Control 5
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL5 CCTL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CCINTEN CCINTEDGE CCOUTINV CCLATCH CCFORCE CCINTSKIP

MODE : CCR Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Compare

Compare Mode

1 : Capture

Capture Mode

End of enumeration elements list.

CCINTEN : CCR Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disabled

CCR interrupt disabled

1 : Enabled

CCR interrupt enabled

End of enumeration elements list.

CCINTEDGE : Capture Mode Interrupt Edge Setting
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : Rising

Rising Edge Interrupt

1 : Falling

Falling Edge Interrupt

2 : Both

Rising and Falling Edge Interrupt

End of enumeration elements list.

CCOUTINV : Invert CCR Output
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Not Inverted

Do not invert CCR output

1 : Inverted

Invert CCR output

End of enumeration elements list.

CCLATCH : CCR Register Latch Mode
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : CTR=0/Rising

Compare(latch on CTR=0)/ Capture(latch on rising edge)

1 : CTR=Period/Falling

Compare(latch on CTR=Period)/ Capture(latch on falling edge)

2 : Immediate/Both

Compare(latch immediately)/ Capture(latch on both edges)

End of enumeration elements list.

CCFORCE : Write 1 to force compare event (self-clearing)
bits : 7 - 14 (8 bit)
access : read-write

CCINTSKIP : CC Interrupt Skip Counter
bits : 8 - 19 (12 bit)
access : read-write

Enumeration:

0 : Don't Skip

Don't skip CCR matches before interrupt

1 : Skip 1

Skip 1 CCR match before interrupt

2 : Skip 2

Skip 2 CCR matches before interrupt

3 : Skip 3

Skip 3 CCR matches before interrupt

4 : Skip 4

Skip 4 CCR matches before interrupt

5 : Skip 5

Skip 5 CCR matches before interrupt

6 : Skip 6

Skip 6 CCR matches before interrupt

7 : Skip 7

Skip 7 CCR matches before interrupt

8 : Skip 8

Skip 8 CCR matches before interrupt

9 : Skip 9

Skip 9 CCR matches before interrupt

10 : Skip 10

Skip 10 CCR matches before interrupt

11 : Skip 11

Skip 11 CCR matches before interrupt

12 : Skip 12

Skip 12 CCR matches before interrupt

13 : Skip 13

Skip 13 CCR matches before interrupt

14 : Skip 14

Skip 14 CCR matches before interrupt

15 : Skip 15

Skip 15 CCR matches before interrupt

End of enumeration elements list.


CCTR5

Timer D CC Counter 5
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTR5 CCTR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCTL6

Timer D CC Control 6
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL6 CCTL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CCINTEN CCINTEDGE CCOUTINV CCLATCH CCFORCE CCINTSKIP

MODE : CCR Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Compare

Compare Mode

1 : Capture

Capture Mode

End of enumeration elements list.

CCINTEN : CCR Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disabled

CCR interrupt disabled

1 : Enabled

CCR interrupt enabled

End of enumeration elements list.

CCINTEDGE : Capture Mode Interrupt Edge Setting
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : Rising

Rising Edge Interrupt

1 : Falling

Falling Edge Interrupt

2 : Both

Rising and Falling Edge Interrupt

End of enumeration elements list.

CCOUTINV : Invert CCR Output
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Not Inverted

Do not invert CCR output

1 : Inverted

Invert CCR output

End of enumeration elements list.

CCLATCH : CCR Register Latch Mode
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : CTR=0/Rising

Compare(latch on CTR=0)/ Capture(latch on rising edge)

1 : CTR=Period/Falling

Compare(latch on CTR=Period)/ Capture(latch on falling edge)

2 : Immediate/Both

Compare(latch immediately)/ Capture(latch on both edges)

End of enumeration elements list.

CCFORCE : Write 1 to force compare event (self-clearing)
bits : 7 - 14 (8 bit)
access : read-write

CCINTSKIP : CC Interrupt Skip Counter
bits : 8 - 19 (12 bit)
access : read-write

Enumeration:

0 : Don't Skip

Don't skip CCR matches before interrupt

1 : Skip 1

Skip 1 CCR match before interrupt

2 : Skip 2

Skip 2 CCR matches before interrupt

3 : Skip 3

Skip 3 CCR matches before interrupt

4 : Skip 4

Skip 4 CCR matches before interrupt

5 : Skip 5

Skip 5 CCR matches before interrupt

6 : Skip 6

Skip 6 CCR matches before interrupt

7 : Skip 7

Skip 7 CCR matches before interrupt

8 : Skip 8

Skip 8 CCR matches before interrupt

9 : Skip 9

Skip 9 CCR matches before interrupt

10 : Skip 10

Skip 10 CCR matches before interrupt

11 : Skip 11

Skip 11 CCR matches before interrupt

12 : Skip 12

Skip 12 CCR matches before interrupt

13 : Skip 13

Skip 13 CCR matches before interrupt

14 : Skip 14

Skip 14 CCR matches before interrupt

15 : Skip 15

Skip 15 CCR matches before interrupt

End of enumeration elements list.


CCTR6

Timer D CC Counter 6
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTR6 CCTR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCTL7

Timer D CC Control 7
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL7 CCTL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CCINTEN CCINTEDGE CCOUTINV CCLATCH CCFORCE CCINTSKIP

MODE : CCR Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Compare

Compare Mode

1 : Capture

Capture Mode

End of enumeration elements list.

CCINTEN : CCR Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disabled

CCR interrupt disabled

1 : Enabled

CCR interrupt enabled

End of enumeration elements list.

CCINTEDGE : Capture Mode Interrupt Edge Setting
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : Rising

Rising Edge Interrupt

1 : Falling

Falling Edge Interrupt

2 : Both

Rising and Falling Edge Interrupt

End of enumeration elements list.

CCOUTINV : Invert CCR Output
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Not Inverted

Do not invert CCR output

1 : Inverted

Invert CCR output

End of enumeration elements list.

CCLATCH : CCR Register Latch Mode
bits : 5 - 11 (7 bit)
access : read-write

Enumeration:

0 : CTR=0/Rising

Compare(latch on CTR=0)/ Capture(latch on rising edge)

1 : CTR=Period/Falling

Compare(latch on CTR=Period)/ Capture(latch on falling edge)

2 : Immediate/Both

Compare(latch immediately)/ Capture(latch on both edges)

End of enumeration elements list.

CCFORCE : Write 1 to force compare event (self-clearing)
bits : 7 - 14 (8 bit)
access : read-write

CCINTSKIP : CC Interrupt Skip Counter
bits : 8 - 19 (12 bit)
access : read-write

Enumeration:

0 : Don't Skip

Don't skip CCR matches before interrupt

1 : Skip 1

Skip 1 CCR match before interrupt

2 : Skip 2

Skip 2 CCR matches before interrupt

3 : Skip 3

Skip 3 CCR matches before interrupt

4 : Skip 4

Skip 4 CCR matches before interrupt

5 : Skip 5

Skip 5 CCR matches before interrupt

6 : Skip 6

Skip 6 CCR matches before interrupt

7 : Skip 7

Skip 7 CCR matches before interrupt

8 : Skip 8

Skip 8 CCR matches before interrupt

9 : Skip 9

Skip 9 CCR matches before interrupt

10 : Skip 10

Skip 10 CCR matches before interrupt

11 : Skip 11

Skip 11 CCR matches before interrupt

12 : Skip 12

Skip 12 CCR matches before interrupt

13 : Skip 13

Skip 13 CCR matches before interrupt

14 : Skip 14

Skip 14 CCR matches before interrupt

15 : Skip 15

Skip 15 CCR matches before interrupt

End of enumeration elements list.


CCTR7

Timer D CC Counter 7
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTR7 CCTR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTGCTL0

Timer D DTG Control 0
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGCTL0 DTGCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTGCTL1

Timer D DTG Control 1
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGCTL1 DTGCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTGCTL2

Timer D DTG Control 2
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGCTL2 DTGCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTGCTL3

Timer D DTG Control 3
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTGCTL3 DTGCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INT

Timer D Interrupt Control
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRD

Timer D Period
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRD PRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CTR

Timer D Counter
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTR CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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