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CAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISR_SR_CMR_MR

ACR

AMR

ALC_TXERR_RXERR_ECC

BTR1_BTR0_RMC_IMR

TXBUF

RXBUF


ISR_SR_CMR_MR

Combined CAN MR, CMR, SR, and ISR registers
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR_SR_CMR_MR ISR_SR_CMR_MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR CMR SR ISR

MR : CAN Mode
bits : 0 - 6 (7 bit)

CMR : CAN Command
bits : 8 - 14 (7 bit)

SR : CAN Status
bits : 16 - 22 (7 bit)

ISR : CAN Interrupt Status/Acknowledge
bits : 24 - 30 (7 bit)


ACR

Combined CAN Acceptance Code registers
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACR0 ACR1 ACR2 ACR3

ACR0 : CAN Acceptance Code 0
bits : 0 - 6 (7 bit)

ACR1 : CAN Acceptance Code 1
bits : 8 - 14 (7 bit)

ACR2 : CAN Acceptance Code 2
bits : 16 - 22 (7 bit)

ACR3 : CAN Acceptance Code 3
bits : 24 - 30 (7 bit)


AMR

Combined CAN Acceptance Mask registers
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMR AMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMR0 AMR1 AMR2 AMR3

AMR0 : CAN Acceptance Mask 0
bits : 0 - 6 (7 bit)

AMR1 : CAN Acceptance Mask 1
bits : 8 - 14 (7 bit)

AMR2 : CAN Acceptance Mask 2
bits : 16 - 22 (7 bit)

AMR3 : CAN Acceptance Mask 3
bits : 24 - 30 (7 bit)


ALC_TXERR_RXERR_ECC

Combined CAN ECC, RXERR, TXERR, and ALC registers
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALC_TXERR_RXERR_ECC ALC_TXERR_RXERR_ECC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECC RXERR TXERR ALC

ECC : CAN Error Code Capture
bits : 0 - 6 (7 bit)

RXERR : CAN RX Error Counter
bits : 8 - 14 (7 bit)

TXERR : CAN TX Error Counter
bits : 16 - 22 (7 bit)

ALC : CAN Arbitration Lost Code Capture
bits : 24 - 30 (7 bit)


BTR1_BTR0_RMC_IMR

Combined CAN IMR, RMC, BTR0, and BTR1 registers
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR1_BTR0_RMC_IMR BTR1_BTR0_RMC_IMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR RMC BTR0 BTR1

IMR : CAN Interrupt Mask
bits : 0 - 6 (7 bit)

RMC : CAN Receive Message Counter
bits : 8 - 14 (7 bit)

BTR0 : CAN Bus Timing Register 0
bits : 16 - 22 (7 bit)

BTR1 : CAN Bus Timing Register 1
bits : 24 - 30 (7 bit)


TXBUF

Combined CAN Transmit Buffer registers
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXBUF TXBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBUF0 TXBUF1 TXBUF2 TXBUF3

TXBUF0 : CAN Transmit Buffer 0
bits : 0 - 6 (7 bit)

TXBUF1 : CAN Transmit Buffer 1
bits : 8 - 14 (7 bit)

TXBUF2 : CAN Transmit Buffer 2
bits : 16 - 22 (7 bit)

TXBUF3 : CAN Transmit Buffer 3
bits : 24 - 30 (7 bit)


RXBUF

Combined CAN Receive Buffer registers
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXBUF RXBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBUF0 RXBUF1 RXBUF2 RXBUF3

RXBUF0 : CAN Receive Buffer 0
bits : 0 - 6 (7 bit)

RXBUF1 : CAN Receive Buffer 1
bits : 8 - 14 (7 bit)

RXBUF2 : CAN Receive Buffer 2
bits : 16 - 22 (7 bit)

RXBUF3 : CAN Receive Buffer 3
bits : 24 - 30 (7 bit)



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