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MEMCTL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

MEMCTL

SWDUNLOCK

FLASHERASE

MEMSTATUS

FLASHLOCK

FLASHPAGE


MEMCTL

Memory Controller Configuration
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMCTL MEMCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WSTATE MCLKDIV WRITEWORDCNT SEIE DEIE INVADDRIE STDBY ECCDIS CACHEDIS MCLKSEL

WSTATE : FLASH Access Wait States
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 0 WS

0 Wait States

1 : 1 WS

1 Wait State

2 : 2 WS

2 Wait States

3 : 3 WS

3 Wait States

4 : 4 WS

4 Wait States

5 : 5 WS

5 Wait States

6 : 6 WS

6 Wait States

7 : 7 WS

7 Wait States

8 : 8 WS

8 Wait States

9 : 9 WS

9 Wait States

10 : 10 WS

10 Wait States

11 : 11 WS

11 Wait States

12 : 12 WS

12 Wait States

13 : 13 WS

13 Wait States

14 : 14 WS

14 Wait States

15 : 15 WS

15 Wait States

End of enumeration elements list.

MCLKDIV : MCLK Divider
bits : 4 - 11 (8 bit)
access : read-write

Enumeration:

0 : HCLK /1

MCLK

1 : HCLK /2

MCLK

2 : HCLK /3

MCLK

3 : HCLK /4

MCLK

4 : HCLK /5

MCLK

5 : HCLK /6

MCLK

6 : HCLK /7

MCLK

7 : HCLK /8

MCLK

8 : HCLK /9

MCLK

9 : HCLK /10

MCLK

10 : HCLK /11

MCLK

11 : HCLK /12

MCLK

12 : HCLK /13

MCLK

13 : HCLK /14

MCLK

14 : HCLK /15

MCLK

15 : HCLK /16

MCLK

End of enumeration elements list.

WRITEWORDCNT : Write Word Data Count
bits : 8 - 17 (10 bit)
access : read-write

SEIE : ECC Single bit Error Interrupt Enable
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : Disabled

ECC Single bit Error Interrupt Disabled

1 : Enabled

ECC Single bit Error Interrupt Enabled

End of enumeration elements list.

DEIE : ECC Dual bit Error Interrupt Enable
bits : 17 - 34 (18 bit)
access : read-write

Enumeration:

0 : Disabled

ECC Dual bit Error Interrupt Disabled

1 : Enabled

ECC Dual bit Error Interrupt Enabled

End of enumeration elements list.

INVADDRIE : Invalid Memory Address Access Interrupt Enable
bits : 18 - 36 (19 bit)
access : read-write

Enumeration:

0 : Disabled

Invalid Memory Interrupt Disabled

1 : Enabled

Invalid Memory Interrupt Enabled

End of enumeration elements list.

STDBY : FLASH Standby Mode
bits : 19 - 38 (20 bit)
access : read-write

Enumeration:

0 : Normal

Normal Mode

1 : Standby

Standby Mode

End of enumeration elements list.

ECCDIS : SRAM ECC Disable
bits : 20 - 40 (21 bit)
access : read-write

Enumeration:

0 : Enabled

SRAM ECC Enabled

1 : Disabled

SRAM ECC Disabled

End of enumeration elements list.

CACHEDIS : FLASH Read Cache Disable
bits : 21 - 42 (22 bit)
access : read-write

Enumeration:

0 : Enabled

FLASH Read Cache Enabled

1 : Disabled

FLASH Read Cache Disabled

End of enumeration elements list.

MCLKSEL : MCLK Mux Select
bits : 22 - 44 (23 bit)
access : read-write

Enumeration:

0 : ROSCCLK

ROSC Clock selected as input to MCLK

1 : MCLK

HCLK / MCLKDIV

End of enumeration elements list.


SWDUNLOCK

SWD Unlock
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWDUNLOCK SWDUNLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASHERASE

FLASH Erase
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASHERASE FLASHERASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MEMSTATUS

Memory Controller Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMSTATUS MEMSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WBUSY EBUSY WRITEWORDCNT SE DE INVADDR

WBUSY : FLASH Write Busy
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Not Busy

FLASH write operation not in progress

1 : Busy

FLASH write operation in progress

End of enumeration elements list.

EBUSY : FLASH Erase Busy
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Not Busy

FLASH erase operation not in progress

1 : Busy

FLASH erase operation in progress

End of enumeration elements list.

WRITEWORDCNT : Write Word Data Count
bits : 8 - 17 (10 bit)
access : read-write

SE : ECC Single bit Error Detection Flag
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : No FLag

No ECC Single bit Error Flag

1 : Flag

ECC Single bit Error Flag Set

End of enumeration elements list.

DE : ECC Dual bit Error Detection Flag
bits : 17 - 34 (18 bit)
access : read-write

Enumeration:

0 : No Flag

No ECC Dual bit Error Flag

1 : Flag

ECC Dual bit Error Flag Set

End of enumeration elements list.

INVADDR : Invalid Memory Address Access Flag
bits : 18 - 36 (19 bit)
access : read-write

Enumeration:

0 : No Flag

No Invalid Memory Flag

1 : Flag

Invalid Memory Flag Set

End of enumeration elements list.


FLASHLOCK

FLASH Lock Access
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASHLOCK FLASHLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASHPAGE

FLASH Page
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASHPAGE FLASHPAGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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