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PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWMCON0

PWM0COM0

PWM0COM1

PWM0COM2

PWM0LEN

PWM1COM0

PWM1COM1

PWM1COM2

PWM1LEN

PWM2COM0

PWM2COM1

PWM2COM2

PWM2LEN

PWMCON1

PWMCLRI


PWMCON0

PWM Control register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMCON0 PWMCON0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE MOD DIR LCOMP HOFF POINV PRE ENA PWMIEN PWM1INV PWM3INV PWM5INV SYNC

ENABLE : Enables all PWM outputs
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

MOD : Enables H-Bridge Mode
bits : 1 - 1 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DIR : Direction Control
bits : 2 - 2 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

LCOMP : Load Compare Registers
bits : 3 - 3 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

HOFF : High Side Off
bits : 4 - 4 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

POINV : Invert all PWM outputs
bits : 5 - 5 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PRE : PWM Clock Prescaler
bits : 6 - 8 (3 bit)

ENA : enable PWM outputs
bits : 9 - 9 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PWMIEN : Enables PWM interrupts
bits : 10 - 10 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PWM1INV : Inversion of PWM output
bits : 11 - 11 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PWM3INV : Inversion of PWM output
bits : 12 - 12 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PWM5INV : Inversion of PWM output
bits : 13 - 13 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

SYNC : PWM Synchronization
bits : 15 - 15 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


PWM0COM0

Compare Register 0 for PWM0 and PWM1
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0COM0 PWM0COM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM0COM1

Compare Register 1 for PWM0 and PWM1
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0COM1 PWM0COM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM0COM2

Compare Register 2 for PWM0 and PWM1
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0COM2 PWM0COM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM0LEN

Period Value register for PWM0 and PWM1
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0LEN PWM0LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM1COM0

Compare Register 0 for PWM2 and PWM3
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM1COM0 PWM1COM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM1COM1

Compare Register 1 for PWM2 and PWM3
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM1COM1 PWM1COM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM1COM2

Compare Register 2 for PWM2 and PWM3
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM1COM2 PWM1COM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM1LEN

Period Value register for PWM2 and PWM3
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM1LEN PWM1LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM2COM0

Compare Register 0 for PWM4 and PWM5
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2COM0 PWM2COM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM2COM1

Compare Register 1 for PWM4 and PWM5
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2COM1 PWM2COM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM2COM2

Compare Register 2 for PWM4 and PWM5
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2COM2 PWM2COM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM2LEN

Period Value register for PWM4 and PWM5
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2LEN PWM2LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWMCON1

Trip control register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMCON1 PWMCON1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CONVSTARTDELAY TRIPEN CONVSTART

CONVSTARTDELAY : ADC conversion start delay configuration
bits : 0 - 3 (4 bit)

TRIPEN : Enable PWM trip functionality
bits : 6 - 6 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

CONVSTART : Enable adc conversion start from pwm
bits : 7 - 7 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


PWMCLRI

PWM interrupt clear. Write to this register clears the latched PWM interrupt.
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMCLRI PWMCLRI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0 PWM1 PWM2 TRIP

PWM0 : Clear the latched PWM0 interrupt
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PWM1 : Clear the latched PWM1 interrupt
bits : 1 - 1 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PWM2 : Clear the latched PWM2 interrupt
bits : 2 - 2 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

TRIP : Clear the latched trip interrupt
bits : 4 - 4 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.



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