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WDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

Registers

T3LD

T3STA

T3VAL

T3CON

T3CLRI


T3LD

Load value.
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T3LD T3LD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Current Value
bits : 0 - 15 (16 bit)


T3STA

Status register, read only.
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T3STA T3STA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ CLRI LD CON LOCK

IRQ : Interrupt Pending
bits : 0 - 0 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

CLRI : T3CLRI write sync in progress
bits : 1 - 1 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

LD : T3LD write sync in progress
bits : 2 - 2 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

CON : T3CON write sync in progress
bits : 3 - 3 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

LOCK : Lock status bit
bits : 4 - 4 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.


T3VAL

Current count value, read only.
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T3VAL T3VAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Current Value
bits : 0 - 15 (16 bit)


T3CON

Control Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T3CON T3CON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD IRQ PRE ENABLE MOD

PD : Power down clear
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

IRQ : Timer Interrupt ,
bits : 1 - 1 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PRE : Prescaler
bits : 2 - 3 (2 bit)

Enumeration:

0 : DIV1

None

1 : DIV16

None

2 : DIV256

None

3 : DIV4096

None

End of enumeration elements list.

ENABLE : Enable
bits : 5 - 5 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

MOD : Mode
bits : 6 - 6 (1 bit)

Enumeration:

0 : FREERUN

None

1 : PERIODIC

None

End of enumeration elements list.


T3CLRI

Clear interrupt, write only.
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T3CLRI T3CLRI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Clear Watchdog
bits : 0 - 15 (16 bit)

Enumeration:

52428 : CLR

None

End of enumeration elements list.



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