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FEE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x84 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FEESTA

FEEADR0L

FEEADR0H

FEEADR1L

FEEADR1H

FEEKEY

FEEPROL

FEEPROH

FEESIGL

FEESIGH

FEECON1

FEECON0

FEEADRAL

FEEADRAH

FEEAEN0

FEEAEN1

FEECMD

FEEAEN2


FEESTA

Status Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEESTA FEESTA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDBUSY WRBUSY CMDDONE WRDONE CMDRES SIGNERR

CMDBUSY : Command busy
bits : 0 - 0 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

WRBUSY : Write busy
bits : 1 - 1 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

CMDDONE : Command complete
bits : 2 - 2 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

WRDONE : Write Complete
bits : 3 - 3 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

CMDRES : Command result
bits : 4 - 5 (2 bit)

Enumeration:

0 : SUCCESS

None

1 : PROTECTED

None

2 : VERIFYERR

None

3 : ABORT

None

End of enumeration elements list.

SIGNERR : Info space signature check on reset error
bits : 6 - 6 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.


FEEADR0L

Low Page (Lower 16 bits)
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEADR0L FEEADR0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Value
bits : 0 - 15 (16 bit)


FEEADR0H

Low Page (Upper 16 bits)
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEADR0H FEEADR0H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Value
bits : 0 - 1 (2 bit)


FEEADR1L

Hi Page (Lower 16 bits)
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEADR1L FEEADR1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Value
bits : 0 - 15 (16 bit)


FEEADR1H

Hi Page (Upper 16 bits)
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEADR1H FEEADR1H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Value
bits : 0 - 1 (2 bit)


FEEKEY

Key
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEKEY FEEKEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Value
bits : 0 - 15 (16 bit)

Enumeration:

62550 : USERKEY1

None

61731 : USERKEY2

None

End of enumeration elements list.


FEEPROL

Write Protection (Lower 16 bits)
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEPROL FEEPROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Value
bits : 0 - 15 (16 bit)


FEEPROH

Write Protection (Upper 16 bits)
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEPROH FEEPROH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Value
bits : 0 - 15 (16 bit)


FEESIGL

Signature (Lower 16 bits)
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEESIGL FEESIGL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Value
bits : 0 - 15 (16 bit)


FEESIGH

Signature (Upper 16 bits)
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEESIGH FEESIGH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Value
bits : 0 - 7 (8 bit)


FEECON1

User Setup register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEECON1 FEECON1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG

DBG : Serial Wire debug enable ,
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


FEECON0

Command Control Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEECON0 FEECON0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IENCMD IENERR WREN

IENCMD : Command complete interrupt enable
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

IENERR : Error interrupt enable
bits : 1 - 1 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

WREN : Write enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


FEEADRAL

Abort address (Lower 16 bits)
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEADRAL FEEADRAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Value
bits : 0 - 15 (16 bit)


FEEADRAH

Abort address (Upper 16 bits)
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEADRAH FEEADRAH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Value
bits : 0 - 15 (16 bit)


FEEAEN0

Lower 16 bits of the sys irq abort enable register.
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEAEN0 FEEAEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T2 EXTINT0 EXTINT1 EXTINT2 EXTINT3 EXTINT4 EXTINT5 EXTINT6 EXTINT7 T3 T0 T1 ADC0 ADC1 SINC2

T2 : TBD
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

EXTINT0 : TBD
bits : 1 - 1 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

EXTINT1 : TBD
bits : 2 - 2 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

EXTINT2 : TBD
bits : 3 - 3 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

EXTINT3 : TBD
bits : 4 - 4 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

EXTINT4 : TBD
bits : 5 - 5 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

EXTINT5 : TBD
bits : 6 - 6 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

EXTINT6 : TBD
bits : 7 - 7 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

EXTINT7 : TBD
bits : 8 - 8 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

T3 : TBD
bits : 9 - 9 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

T0 : TBD
bits : 11 - 11 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

T1 : TBD
bits : 12 - 12 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

ADC0 : TBD
bits : 13 - 13 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

ADC1 : TBD
bits : 14 - 14 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

SINC2 : TBD
bits : 15 - 15 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


FEEAEN1

Upper 16 bits of the sys irq abort enable register.
address_offset : 0x7C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEAEN1 FEEAEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEE UART SPI0 SPI1 I2CS I2CM DMAERROR DMASPI1TX DMASPI1RX DMAUARTTX DMAUARTRX DMAI2CSTX DMAI2CSRX DMAI2CMTX DMAI2CMRX DMADAC

FEE : TBD
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

UART : TBD
bits : 1 - 1 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

SPI0 : TBD
bits : 2 - 2 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

SPI1 : TBD
bits : 3 - 3 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

I2CS : TBD
bits : 4 - 4 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

I2CM : TBD
bits : 5 - 5 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMAERROR : TBD
bits : 6 - 6 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMASPI1TX : TBD
bits : 7 - 7 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMASPI1RX : TBD
bits : 8 - 8 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMAUARTTX : TBD
bits : 9 - 9 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMAUARTRX : TBD
bits : 10 - 10 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMAI2CSTX : TBD
bits : 11 - 11 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMAI2CSRX : TBD
bits : 12 - 12 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMAI2CMTX : TBD
bits : 13 - 13 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMAI2CMRX : TBD
bits : 14 - 14 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMADAC : TBD
bits : 15 - 15 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


FEECMD

Command register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEECMD FEECMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD

CMD : Command
bits : 0 - 3 (4 bit)

Enumeration:

0 : IDLE

- No command executed

1 : ERASEPAGE

- Erase Page

2 : SIGN

- Sign Range

3 : MASSERASE

- Mass Erase User Space

4 : ABORT

- Abort a running command

End of enumeration elements list.


FEEAEN2

Upper 32..47 bits of the sys irq abort enable register.
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEEAEN2 FEEAEN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADC0 DMAADC1 DMASINC2 PWMTRIP PWM0 PWM1 PWM2

DMAADC0 : TBD
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMAADC1 : TBD
bits : 1 - 1 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DMASINC2 : TBD
bits : 2 - 2 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PWMTRIP : TBD
bits : 3 - 3 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PWM0 : TBD
bits : 4 - 4 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PWM1 : TBD
bits : 5 - 5 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

PWM2 : TBD
bits : 6 - 6 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.



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