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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection :

Registers

I2CMCON

I2CMRXCNT

I2CMCRXCNT

I2CADR0

I2CADR1

I2CDIV

I2CSCON

I2CSSTA

I2CSRX

I2CSTX

I2CALT

I2CID0

I2CMSTA

I2CID1

I2CID2

I2CID3

I2CFSTA

I2CMRX

I2CMTX


I2CMCON

Master Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CMCON I2CMCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAS COMPETE LOOPBACK STRETCH IENRX IENTX IENALOST IENNACK IENCMP RXDMA TXDMA

MAS : Master Enable
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

COMPETE : Compete for ownership
bits : 1 - 1 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

LOOPBACK : Internal loop back
bits : 2 - 2 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

STRETCH : Stretch SCL
bits : 3 - 3 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

IENRX : Receive request interrupt enable
bits : 4 - 4 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

IENTX : Transmit request interrupt enable
bits : 5 - 5 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

IENALOST : Arbitration lost interrupt enable
bits : 6 - 6 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

IENNACK : ACK not received interrupt enable
bits : 7 - 7 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

IENCMP : Transaction completed interrupt enable
bits : 8 - 8 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

RXDMA : Enable master Rx DMA request
bits : 10 - 10 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

TXDMA : Enable master Tx DMA request
bits : 11 - 11 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


I2CMRXCNT

Master Receive Data Count
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CMRXCNT I2CMRXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT EXTEND

COUNT : Receive count
bits : 0 - 7 (8 bit)

EXTEND : Extended Read
bits : 8 - 8 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


I2CMCRXCNT

Master Current Receive Data Count
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CMCRXCNT I2CMCRXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Current Receive count
bits : 0 - 7 (8 bit)


I2CADR0

1st Master Address Byte
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CADR0 I2CADR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE

VALUE : Address byte
bits : 0 - 7 (8 bit)


I2CADR1

2nd Master Address Byte
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CADR1 I2CADR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE

VALUE : Address byte
bits : 0 - 7 (8 bit)


I2CDIV

Serial clock period divisor register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CDIV I2CDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOW HIGH

LOW : Low Time
bits : 0 - 7 (8 bit)

HIGH : High Time
bits : 8 - 15 (8 bit)


I2CSCON

Slave Control Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CSCON I2CSCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLV ADR10 GC HGC GCSB EARLYTXR STRETCH NACK IENSTOP IENRX IENTX IENREPST RXDMA TXDMA

SLV : Slave Enable
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

ADR10 : Enable 10 bit addressing
bits : 1 - 1 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

GC : General Call enable
bits : 2 - 2 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

HGC : Hardware general Call enable
bits : 3 - 3 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

GCSB : General call status bit clear
bits : 4 - 4 (1 bit)

Enumeration:

1 : CLR

None

End of enumeration elements list.

EARLYTXR : Early transmit request mode
bits : 5 - 5 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

STRETCH : Stretch SCL
bits : 6 - 6 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

NACK : NACK next communication
bits : 7 - 7 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

IENSTOP : Stop condition detected interrupt enable
bits : 8 - 8 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

IENRX : Receive request interrupt enable
bits : 9 - 9 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

IENTX : Transmit request interrupt enable
bits : 10 - 10 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

IENREPST : Repeated start interrupt enable
bits : 12 - 12 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

RXDMA : Enable slave Rx DMA request
bits : 13 - 13 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

TXDMA : Enable slave Tx DMA request
bits : 14 - 14 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


I2CSSTA

Slave I2C Status, Error and IRQ Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CSSTA I2CSSTA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFSEREQ TXUR TXREQ RXREQ RXOF NOACK BUSY GCINT GCID STOP IDMAT REPSTART START

TXFSEREQ : Tx FIFO status or early request
bits : 0 - 0 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

TXUR : Transmit FIFO underflow
bits : 1 - 1 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

TXREQ : Transmit
bits : 2 - 2 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

RXREQ : Receive
bits : 3 - 3 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

RXOF : Receive FIFO
bits : 4 - 4 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

NOACK : Ack not generated by the slave
bits : 5 - 5 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

BUSY : Slave busy
bits : 6 - 6 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

GCINT : General call
bits : 7 - 7 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

GCID : General ID
bits : 8 - 9 (2 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

STOP : Stop after start and matching address
bits : 10 - 10 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

IDMAT : Device ID matched
bits : 11 - 12 (2 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

REPSTART : Repeated start and matching address
bits : 13 - 13 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

START : Start and matching address
bits : 14 - 14 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.


I2CSRX

Slave Receive Data Register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CSRX I2CSRX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Receive register
bits : 0 - 7 (8 bit)


I2CSTX

Slave Transmit Data Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CSTX I2CSTX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Transmit register
bits : 0 - 7 (8 bit)


I2CALT

Hardware General Call ID
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CALT I2CALT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Alt register
bits : 0 - 7 (8 bit)


I2CID0

1st Slave Address Device ID
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CID0 I2CID0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Slave ID
bits : 0 - 7 (8 bit)


I2CMSTA

Master Status Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CMSTA I2CMSTA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFSTA TXREQ RXREQ NACKADDR ALOST BUSY NACKDATA TCOMP RXOF LINEBUSY MSTOP TXUR

TXFSTA : Transmit FIFO Status
bits : 0 - 1 (2 bit)

Enumeration:

0 : EMPTY

None

1 : ONEBYTE

None

3 : FULL

None

End of enumeration elements list.

TXREQ : Transmit request
bits : 2 - 2 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

RXREQ : Receive request
bits : 3 - 3 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

NACKADDR : Ack not received in response to an address
bits : 4 - 4 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

ALOST : Arbitration lost
bits : 5 - 5 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

BUSY : Master Busy
bits : 6 - 6 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

NACKDATA : Ack not received in response to data write
bits : 7 - 7 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

TCOMP : Transaction completed
bits : 8 - 8 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

RXOF : Receive FIFO overflow
bits : 9 - 9 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

LINEBUSY : Line is busy
bits : 10 - 10 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

MSTOP : STOP driven by th eI2C master
bits : 11 - 11 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.

TXUR : Master Transmit FIFO underflow
bits : 12 - 12 (1 bit)

Enumeration:

0 : CLR

None

1 : SET

None

End of enumeration elements list.


I2CID1

2nd Slave Address Device ID
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CID1 I2CID1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Slave ID
bits : 0 - 7 (8 bit)


I2CID2

3rd Slave Address Device ID
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CID2 I2CID2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Slave ID
bits : 0 - 7 (8 bit)


I2CID3

4th Slave Address Device ID
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CID3 I2CID3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Slave ID
bits : 0 - 7 (8 bit)


I2CFSTA

Master and Slave Rx/Tx FIFO Status Register
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CFSTA I2CFSTA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STXFSTA SRXFSTA MTXFSTA MRXFSTA SFLUSH MFLUSH

STXFSTA : Slave Transmit FIFO Status
bits : 0 - 1 (2 bit)

Enumeration:

0 : EMPTY

None

1 : ONEBYTE

None

2 : TWOBYTES

None

End of enumeration elements list.

SRXFSTA : Slave receive FIFO Status
bits : 2 - 3 (2 bit)

Enumeration:

0 : EMPTY

None

1 : ONEBYTE

None

2 : TWOBYTES

None

End of enumeration elements list.

MTXFSTA : Master Transmit FIFO Status
bits : 4 - 5 (2 bit)

Enumeration:

0 : EMPTY

None

1 : ONEBYTE

None

2 : TWOBYTES

None

End of enumeration elements list.

MRXFSTA : Master receive FIFO Status
bits : 6 - 7 (2 bit)

Enumeration:

0 : EMPTY

None

1 : ONEBYTE

None

2 : TWOBYTES

None

End of enumeration elements list.

SFLUSH : Flush the slave transmit FIFO
bits : 8 - 8 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

MFLUSH : Flush the master transmit FIFO
bits : 9 - 9 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


I2CMRX

Master Receive Data
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CMRX I2CMRX read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE

VALUE : Current Receive Value
bits : 0 - 7 (8 bit)


I2CMTX

Master Transmit Data
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CMTX I2CMTX read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE

VALUE : Current Transmit Value
bits : 0 - 7 (8 bit)



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