Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
Status Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ : Interrupt status bit
bits : 0 - 0 (1 bit)
Enumeration:
0 : CLR
None
1 : SET
None
End of enumeration elements list.
TXFSTA : transmit FIFO Status
bits : 1 - 3 (3 bit)
Enumeration:
0 : EMPTY
None
1 : ONEBYTE
None
2 : TWOBYTES
None
3 : THREEBYTES
None
4 : FOURBYTES
None
End of enumeration elements list.
TXUR : Transmit FIFO underflow
bits : 4 - 4 (1 bit)
Enumeration:
0 : CLR
None
1 : SET
None
End of enumeration elements list.
TX : Set when a transmit interrupt occurs
bits : 5 - 5 (1 bit)
Enumeration:
0 : CLR
None
1 : SET
None
End of enumeration elements list.
RX : Set when a receive interrupt occurs
bits : 6 - 6 (1 bit)
Enumeration:
0 : CLR
None
1 : SET
None
End of enumeration elements list.
RXOF : Receive FIFO overflow
bits : 7 - 7 (1 bit)
Enumeration:
0 : CLR
None
1 : SET
None
End of enumeration elements list.
RXFSTA : Receive FIFO Status
bits : 8 - 10 (3 bit)
Enumeration:
0 : EMPTY
None
1 : ONEBYTE
None
2 : TWOBYTES
None
3 : THREEBYTES
None
4 : FOURBYTES
None
End of enumeration elements list.
RXS : Set when there are more bytes in the RX FIFO than the TIM bit says
bits : 11 - 11 (1 bit)
Enumeration:
0 : CLR
None
1 : SET
None
End of enumeration elements list.
CSERR : Detected an abrupt CS deassertion
bits : 12 - 12 (1 bit)
Enumeration:
0 : CLR
None
1 : SET
None
End of enumeration elements list.
16-bit configuration register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : SPI Enable bit
bits : 0 - 0 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
MASEN : Master enable
bits : 1 - 1 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
CPHA : Clock phase mode
bits : 2 - 2 (1 bit)
Enumeration:
0 : SAMPLELEADING
None
1 : SAMPLETRAILING
None
End of enumeration elements list.
CPOL : Clock polarity mode
bits : 3 - 3 (1 bit)
Enumeration:
0 : LOW
None
1 : HIGH
None
End of enumeration elements list.
WOM : Wired OR enable
bits : 4 - 4 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
LSB : LSB First Transfer enable
bits : 5 - 5 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
TIM : Transfer and interrupt mode
bits : 6 - 6 (1 bit)
Enumeration:
0 : RXRD
- Cleared by user to initiate transfer with a read of the SPIRX register
1 : TXWR
- Set by user to initiate transfer with a write to the SPITX register.
End of enumeration elements list.
ZEN : Transmit zeros when empty
bits : 7 - 7 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
RXOF : RX Oveflow Overwrite enable
bits : 8 - 8 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
SOEN : Slave MISO output enable bit
bits : 9 - 9 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
LOOPBACK : Loopback enable bit
bits : 10 - 10 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
CON : Continuous transfer enable
bits : 11 - 11 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
RFLUSH : RX FIFO Flush Enable bit
bits : 12 - 12 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
TFLUSH : TX FIFO Flush Enable bit
bits : 13 - 13 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
MOD : SPI IRQ Mode bits
bits : 14 - 15 (2 bit)
Enumeration:
0 : TX1RX1
None
1 : TX2RX2
None
2 : TX3RX3
None
3 : TX4RX4
None
End of enumeration elements list.
DMA enable register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable DMA for data transfer
bits : 0 - 0 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
IENTXDMA : Enable transmit DMA request
bits : 1 - 1 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
IENRXDMA : Enable receive DMA request
bits : 2 - 2 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
8-bit received byte count register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Count
bits : 0 - 7 (8 bit)
8-bit Receive register.
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Received data
bits : 0 - 7 (8 bit)
8-bit Transmit register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Data to transmit
bits : 0 - 7 (8 bit)
SPI Clock Divider Registers
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Factor used to divide UCLK to generate the serial clock
bits : 0 - 5 (6 bit)
BCRST : Bit counter reset
bits : 7 - 7 (1 bit)
Enumeration:
0 : DIS
None
1 : EN
None
End of enumeration elements list.
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