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TMR_RGB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected

Registers

LOAD

CAPTURE

ALOAD

ACURCNT

STAT

PWM0CTL

PWM0MATCH

EVENTSELECT

PWM1CTL

PWM1MATCH

PWM2CTL

PWM2MATCH

CURCNT

CTL

CLRINT


LOAD

16-bit load value
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOAD LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Load value
bits : 0 - 15 (16 bit)
access : read-write


CAPTURE

Capture
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPTURE CAPTURE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : 16-bit captured value
bits : 0 - 15 (16 bit)
access : read-only


ALOAD

16-bit load value, asynchronous
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALOAD ALOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Load value, asynchronous
bits : 0 - 15 (16 bit)
access : read-write


ACURCNT

16-bit timer value, asynchronous
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACURCNT ACURCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Counter value
bits : 0 - 15 (16 bit)
access : read-only


STAT

Status
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUT CAPTURE BUSY PDOK CNTRST

TIMEOUT : Timeout event occurred
bits : 0 - 0 (1 bit)
access : read-only

CAPTURE : Capture event pending
bits : 1 - 1 (1 bit)
access : read-only

BUSY : Timer Busy
bits : 6 - 6 (1 bit)
access : read-only

PDOK : Clear Interrupt Register synchronization
bits : 7 - 7 (1 bit)
access : read-only

CNTRST : Counter reset occurring
bits : 8 - 8 (1 bit)
access : read-only


PWM0CTL

PWM0 Control Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0CTL PWM0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH IDLESTATE

MATCH : PWM Match enabled
bits : 0 - 0 (1 bit)
access : read-write

IDLESTATE : PWM Idle State
bits : 1 - 1 (1 bit)
access : read-write


PWM0MATCH

PWM0 Match Value
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0MATCH PWM0MATCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : PWM Match Value
bits : 0 - 15 (16 bit)
access : read-write


EVENTSELECT

Timer Event selection Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTSELECT EVENTSELECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVTRANGE

EVTRANGE : Event select range
bits : 0 - 5 (6 bit)
access : read-write


PWM1CTL

PWM1 Control Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM1CTL PWM1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH IDLESTATE

MATCH : PWM Match enabled
bits : 0 - 0 (1 bit)
access : read-write

IDLESTATE : PWM Idle State
bits : 1 - 1 (1 bit)
access : read-write


PWM1MATCH

PWM1 Match Value
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM1MATCH PWM1MATCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : PWM Match Value
bits : 0 - 15 (16 bit)
access : read-write


PWM2CTL

PWM2 Control Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2CTL PWM2CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH IDLESTATE

MATCH : PWM Match enabled
bits : 0 - 0 (1 bit)
access : read-write

IDLESTATE : PWM Idle State
bits : 1 - 1 (1 bit)
access : read-write


PWM2MATCH

PWM2 Match Value
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2MATCH PWM2MATCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : PWM Match Value
bits : 0 - 15 (16 bit)
access : read-write


CURCNT

16-bit timer value
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CURCNT CURCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Current count
bits : 0 - 15 (16 bit)
access : read-only


CTL

Control
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRE UP MODE EN CLK RLD EVTEN RSTEN SYNCBYP

PRE : Prescaler
bits : 0 - 1 (2 bit)
access : read-write

UP : Count up
bits : 2 - 2 (1 bit)
access : read-write

MODE : Timer mode
bits : 3 - 3 (1 bit)
access : read-write

EN : Timer enable
bits : 4 - 4 (1 bit)
access : read-write

CLK : Clock select
bits : 5 - 6 (2 bit)
access : read-write

RLD : Reload control
bits : 7 - 7 (1 bit)
access : read-write

EVTEN : Event select
bits : 13 - 13 (1 bit)
access : read-write

RSTEN : Counter and prescale reset enable
bits : 14 - 14 (1 bit)
access : read-write

SYNCBYP : Synchronization bypass
bits : 15 - 15 (1 bit)
access : read-write


CLRINT

Clear interrupt
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLRINT CLRINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUT EVTCAPT

TIMEOUT : Clear timeout interrupt
bits : 0 - 0 (1 bit)
access : write-only

EVTCAPT : Clear captured event interrupt
bits : 1 - 1 (1 bit)
access : write-only



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